Multi-Tier 3D Memory Shared Buried Source Lines
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently accessing and interconnecting multiple tiers of vertical semiconductor channels, leading to limitations in density and scalability.
Innovation Solution
A multi-tier memory device structure is developed, featuring alternating stacks of insulating and conductive layers with shared buried source lines and inter-tier dielectric material layers, allowing for electrical shorting between tiers and enhanced interconnectivity through bit lines and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional three-dimensional memory devices are used with separate source lines for each tier, then each tier can be independently accessed, but the device complexity and interconnection requirements increase significantly
Solution Approach 1:
The patent merges the source line functions across multiple tiers by implementing a shared buried source line that serves both the first tier and second tier simultaneously. This consolidation reduces the number of separate source lines needed, simplifying the interconnection structure while maintaining the ability to access different tiers through their respective bit lines and select gates.
Solution Approach 2:
The shared buried source line performs multiple functions: it serves as the source for first-tier vertical channels, connects to second-tier vertical channels through electrical shorts, and provides a common reference potential for multiple memory stacks. This multi-functional design reduces complexity while preserving tier access independence.
2Quantity of substance
If more tiers are added to increase memory density, then storage capacity improves, but the difficulty of interconnecting and accessing all tiers increases
Solution Approach 1:
The patent transitions from a two-dimensional planar interconnection approach to a three-dimensional vertical architecture where source lines are buried beneath multiple tiers. This allows tiers to be stacked vertically with shared underlying infrastructure, enabling density scaling without proportionally increasing interconnection complexity.
Solution Approach 2:
The structure nests multiple tiers above a shared buried source line, with the source line positioned at a lower level serving multiple upper tiers. This nested arrangement allows second-tier channels to electrically short to the shared source line while first-tier channels also connect to it, creating a compact hierarchical interconnection scheme.
3Device complexity
If shared buried source lines are implemented to reduce complexity, then interconnection structure simplifies, but manufacturing precision requirements increase
Solution Approach 1:
The shared buried source line is formed early in the manufacturing process before the vertical channels and interconnect structures are created. This preliminary formation allows subsequent steps to build upon a established reference structure, and electrical shorts to the source line can be precisely controlled during the channel formation process.
Solution Approach 2:
The patent introduces intermediate dielectric layers and spacer structures that mediate between the shared buried source line and the vertical channels. These intermediary elements provide controlled spacing and electrical isolation where needed, while allowing precise electrical shorts to be formed at specific locations through controlled dielectric removal or direct contact during fabrication.
Data Source
AI summary
A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.