Multi-Tier SiP Assembly With Modular Interconnect Routing
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Solution Overview
Problem
Current multi-tier system-in-package (SiP) modules face challenges in construction complexity and limited signal routing density, necessitating improved methods for integration and device performance.
Innovation Solution
A streamlined process for forming multi-tier SiP modules involves stacking substrates with conductive and insulating layers, using pick-and-place machines for component placement, and forming interconnects with solder bumps and shielding layers to enhance electrical and mechanical connections, while reducing manufacturing costs and package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multi-tier SiP modules are constructed with traditional methods, then device functionality is achieved, but construction complexity increases and signal routing density is limited
Solution Approach 1:
The patent divides the multi-tier SiP module into distinct tiers or levels, with each tier containing specific functional components. This segmentation allows for modular construction, where each tier can be independently fabricated, tested, and assembled, thereby reducing overall construction complexity while maintaining reliability through systematic organization of complex functions across multiple manageable layers
Solution Approach 2:
The patent implements a nested structure where multiple tiers are stacked vertically, with each tier containing components and interconnects that are integrated within the three-dimensional space. This nesting approach allows high-density integration of multiple functional layers without proportionally increasing construction complexity, as the nested architecture provides a systematic framework for organizing and assembling complex multi-tier systems
2Quantity of substance
If traditional SiP topologies are used, then current device requirements are met, but signal routing density reaches its limit
Solution Approach 1:
The patent transitions from traditional two-dimensional planar routing to three-dimensional vertical routing across multiple tiers. By utilizing the vertical dimension and stacking tiers with interconnects between them, the system achieves significantly higher signal routing density without proportionally increasing topology complexity, as the vertical intertier connections provide efficient pathways that reduce the burden on individual tier routing
3Quantity of substance
If advanced multi-tier integration methods are implemented, then integration density increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs preliminary actions by pre-fabricating individual tiers with their components and interconnects before final assembly. This allows for standardized manufacturing processes on each tier, simplifying the overall manufacturing complexity while achieving high integration density. The pre-prepared tiers can be mass-produced using optimized processes and then systematically assembled into the final multi-tier configuration
Solution Approach 2:
The patent implements universal interconnect structures and standardized tier designs that can be reused across multiple devices and configurations. This universality allows high integration density to be achieved through repetitive, standardized manufacturing steps rather than custom complex processes for each device, thereby maintaining manufacturing ease while increasing integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in higher integration density, improved performance, and a smaller form factor for semiconductor packages with increased reliability and reduced manufacturing costs compared to prior art.
Implementation Method 1
forming interconnects with solder bumps
Implementation Method 2
forming interconnects with solder bumps
Implementation Method 3
The encapsulant material provides physical support and electrical isolation
Data Source
AI summary
A semiconductor device has a first substrate and a first electrical component disposed over a first surface of the first substrate. A first encapsulant is deposited over the first electrical component and first surface of the first substrate. A modular interconnect unit is disposed over a second surface of the first substrate. A second encapsulant is deposited over the second surface of the first substrate. A second substrate is disposed over the second surface of the first substrate and electrically connected to the first substrate through the modular interconnect unit.