Multi-Tier Solder Resist Structure for Conductive Bump Separation

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Solution Overview

Problem

As integrated circuits (ICs) evolve with smaller feature sizes and larger footprints, substrate warpage can cause conductive bumps to short or bridge, leading to manufacturing failures and reduced reliability.

Innovation Solution

A multi-tier solder resist structure made of dielectric material, such as epoxy or polymer, is used between adjacent conductive bumps, with varying widths at different heights to prevent bridging and shorting, ensuring better connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If substrate warpage is present during IC manufacturing, then manufacturing complexity increases, but conductive bumps may short or bridge leading to reduced reliability

Engineering Contradiction:
Improveconductive bump connectivityVSAvoidsolder resist structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The solder resist structure is divided into multiple tiers (first tier, second tier, third tier) with each tier having different widths. This segmentation allows the structure to accommodate substrate warpage while maintaining proper spacing between conductive bumps, preventing shorting and bridging issues.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces a vertical dimension by creating multi-tiered solder resist structures at different heights above the substrate. This dimensional approach allows the solder resist to adapt to substrate warpage without increasing lateral complexity, effectively preventing conductive bump failures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If feature sizes are reduced to increase IC functionality, then processing power increases, but solder bridge risk increases due to smaller spacing

Engineering Contradiction:
ImproveIC processing powerVSAvoidsolder joint integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By extending the solder resist structure into the vertical dimension with multiple tiers, the invention provides additional spacing control between conductive bumps without reducing their horizontal density. This allows smaller feature sizes to be used while maintaining solder joint integrity through the multi-level resist structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The multi-tier solder resist structure provides localized spacing control between conductive bumps where needed most. Each tier can be optimized independently to provide appropriate clearance for specific bump configurations, enabling higher density layouts while preventing solder bridges.

Inventive Principle:
Principle #3Local quality

3Reliability

If multi-tier solder resist structure is implemented, then bridging prevention improves, but manufacturing process complexity increases

Engineering Contradiction:
Improveconductive bump separationVSAvoidsolder resist fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The solder resist fabrication process is segmented into multiple deposition and patterning steps, with each tier being formed separately. This segmentation allows for better process control and quality assurance at each stage, making the complex multi-tier structure manufacturable through standardized semiconductor fabrication processes.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11967547B2Solder resist structure to mitigate solder bridge risk
Publication Date: 2024.04.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11967547B2 patent drawing
  • US11967547B2 patent drawing
  • US11967547B2 patent drawing

AI summary

Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.