Multi-tier Trace Architecture for High Bandwidth Data Separation

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Solution Overview

Problem

Conventional trace units in computer processing systems have limited bandwidth, making it difficult to observe long history traces and are costly to extend, especially for multi-core devices, and they cannot easily separate high and low bandwidth trace information for efficient data output.

Innovation Solution

A multi-tier trace architecture that separates trace data into low bandwidth and high bandwidth paths, with an on-chip buffer for high bandwidth data and an off-chip interface for low bandwidth data, allowing for parallel output and reducing the need for additional observation units and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional trace units use a single trace stream for packed trace messages, then the architecture is simple, but the bandwidth is limited and cannot support long history traces

Engineering Contradiction:
Improvetrace architecture complexityVSAvoidtrace bandwidth
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the single trace stream into multiple separate trace streams (first trace stream for program flow, second trace stream for data accesses). This segmentation allows each stream to be optimized for its specific purposes, enabling higher bandwidth for data trace while maintaining simplicity for program flow trace.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension by adding multiple trace streams parallel to the existing single stream architecture. This dimensional expansion from 1D (single stream) to 2D (multiple streams) enables the system to handle longer history traces with higher bandwidth without proportionally increasing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If trace bandwidth is increased to observe long history traces, then more trace information can be captured, but the chip area and cost increase significantly

Engineering Contradiction:
Improvetrace history lengthVSAvoidchip area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

By segmenting trace data into program flow traces and data access traces separated into different streams, the system can selectively allocate resources. The data access stream can use higher bandwidth when needed without requiring the entire trace infrastructure to be oversized, thus reducing overall chip area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements partial trace observation by selectively tracing only data accesses that meet certain criteria (e.g., address range qualifications) rather than tracing all possible activities. This partial action approach reduces the required bandwidth and chip area while still capturing sufficient information for debugging.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If a single trace stream is used for all trace data, then the architecture is simple, but it cannot separate high bandwidth and low bandwidth trace information for efficient output

Engineering Contradiction:
Improvetrace path configurationVSAvoiddata output efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the trace output into separate paths: a first path for program flow traces and a second path for data access traces. This segmentation enables independent optimization of each path, allowing efficient output of different trace types without requiring a complex unified path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each trace stream is given local quality characteristics appropriate to its content - program flow traces use one set of output parameters while data access traces use different parameters optimized for their specific needs. This local optimization improves overall output efficiency without requiring a completely redesigned architecture.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9164868B2Multi-tier trace
Publication Date: 2015.10.20 INFINEON TECHNOLOGIES AG
  • US9164868B2 patent drawing
  • US9164868B2 patent drawing
  • US9164868B2 patent drawing

AI summary

The disclosure relates to methods and systems for trace solutions in a computer processing system. More specifically, the disclosure relates to methods and systems for a multi-tier trace architecture. A method for separating raw trace data includes receiving raw trace data from one of more CPUs and/or busses in the system, separating the raw trace data into high bandwidth trace information (HBTI) and low bandwidth trace information (LBTI), recording the HBTI on an on-chip trace buffer until a specific event is triggered, and providing in parallel the LBTI over an off-chip trace interface. In one embodiment, the raw trace data are provided to a separate HBTI trace unit and a separate LBTI respectively. The HBTI trace unit processes the HBTI and generates a HBTI message, and the LBTI trace unit processes the LBTI and generates a LBTI message.