Multi-Tier Deep Trench Capacitor for High Capacitance Density
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Solution Overview
Problem
Existing capacitors in semiconductor chips require significant device area for high capacitance, limiting their integration and efficiency.
Innovation Solution
A multi-tier deep trench capacitor structure is developed, where multiple capacitor assemblies are stacked to increase capacitance without increasing lateral dimensions, utilizing a semiconductor substrate with vertically extending deep trenches filled with alternating metallic electrode and dielectric layers, and bonded to form a compact high-capacitance structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor structures are used, then high capacitance is achieved, but device area occupied is large
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional deep trench structures. Capacitors are formed by etching deep trenches into the substrate and filling them with alternating metallic electrode and dielectric layers, utilizing the vertical dimension to increase capacitance density without proportionally increasing lateral device area.
Solution Approach 2:
Multiple capacitor assemblies are stacked vertically to form multi-tier structures. Each tier consists of deep trenches filled with nested alternating layers of metallic electrodes and dielectric materials, with subsequent tiers stacked above previous ones, creating a compact nested arrangement that maximizes capacitance within limited space.
2Area of stationary object
If multi-tier deep trench capacitor structure is used, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The capacitor structure is divided into multiple discrete tiers, each containing segmented deep trenches filled with alternating layers. This segmentation allows for modular manufacturing where each tier can be formed and assembled systematically, managing the complexity of the three-dimensional structure through staged fabrication processes.
Solution Approach 2:
By moving to three-dimensional deep trench structures with vertical stacking, the patent reduces lateral device area occupation. The increased vertical complexity is managed through systematic layer-by-layer fabrication and stacking processes, trading lateral space for vertical arrangement.
Data Source
AI summary
A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.