Multi-Tile GPU Work Partitioning for Compute Optimization

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Solution Overview

Problem

Current graphics processing systems are limited in utilizing multiple tiles for workload assignment, leading to suboptimal performance in graphics processing and machine-learning operations.

Innovation Solution

A multi-tile partitioned walker is implemented to optimize compute tasks by efficiently distributing workloads across multiple graphics processing units (GPUs), allowing for improved parallel processing and resource allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple tiles are implemented in the graphics processor, then processing capacity and parallelism are improved, but the ability to utilize these tiles for workload assignment is insufficient

Engineering Contradiction:
Improveprocessing capacityVSAvoidworkload assignment capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The graphics processor is divided into multiple independent tiles, each capable of executing workloads independently. The patent implements a tile-based architecture where each tile contains its own processing units and can be assigned specific workloads, enabling parallel processing while maintaining individual tile autonomy for flexible workload distribution

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of workload management by implementing a multi-tile assignment mechanism that operates at the tile level rather than the traditional processor level. This dimensional change in workload assignment enables finer-grained control and better utilization of multiple tiles for both graphics and machine-learning operations

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If fixed function computational units are used, then specific graphics operations are processed efficiently, but the processor cannot support a wider variety of operations

Engineering Contradiction:
Improveoperation speedVSAvoidoperation variety
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements universal computational units within each tile that can be dynamically configured to perform different types of operations. These units support both traditional graphics processing and machine-learning workloads, replacing fixed-function units with reconfigurable processors that maintain high performance across diverse operation types

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20220138895A1Compute optimization in graphics processing
Publication Date: 2022.05.05 INTEL CORP
  • US20220138895A1 patent drawing
  • US20220138895A1 patent drawing
  • US20220138895A1 patent drawing

AI summary

Embodiments are generally directed to compute optimization in graphics processing. An embodiment of an apparatus includes one or more processors including a multi-tile graphics processing unit (GPU) to process data, the multi-tile GPU including multiple processor tiles; and a memory for storage of data for processing, wherein the apparatus is to receive compute work for processing by the GPU, partition the compute work into multiple work units, assign each of multiple work units to one of the processor tiles, and process the compute work using the processor tiles assigned to the work units.