Multi-Tile Motherboard Tester for Parallel DRAM Testing
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Solution Overview
Problem
Current memory test systems for DRAM components are costly, complex, and prone to damaging the components due to the need for multiple handling and expensive tooling, with existing methods requiring multiple test systems and handling at different temperatures.
Innovation Solution
A tester board system with multiple motherboards mounted on a sturdy frame, allowing for simultaneous testing of multiple DRAM components with a microclimate chamber for temperature control and electrical connectivity, reducing the need for multiple test systems and handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate test systems are used for BI test, weak cell test, and speed test at different temperatures, then comprehensive testing coverage is achieved, but handling damage to contacts increases and system cost increases
Solution Approach 1:
The patent combines multiple separate test systems (BI test system, weak cell test system, speed test system) into a single integrated test system. This integration allows all tests to be performed on the same platform without removing components between tests, thereby eliminating handling damage to contact balls while maintaining comprehensive testing coverage across all memory types and temperatures.
Solution Approach 2:
The test system is designed with universal functionality to perform multiple types of tests (BI test, weak cell test, speed test) on various memory components (DRAM, Flash, etc.) simultaneously. The system includes multiple test heads and temperature chambers that can accommodate different component types and test requirements, eliminating the need for separate specialized test systems.
2Reliability
If multiple separate test systems are used for BI test, weak cell test, and speed test, then comprehensive testing coverage is achieved, but system cost and complexity increase
Solution Approach 1:
The patent consolidates multiple expensive separate test systems into a single integrated platform, reducing overall system cost and complexity while maintaining comprehensive testing capabilities. The integrated system shares common infrastructure such as temperature chambers, control systems, and mechanical handling mechanisms across all test functions.
Solution Approach 2:
The system employs universal test heads and configurable test channels that can be programmed to perform different test types (BI, weak cell, speed tests) on various memory components. This multi-functionality eliminates the need for multiple specialized test systems, significantly reducing system cost and complexity.
3Temperature
If components are tested at different temperatures by removing and retesting on different systems, then temperature-specific testing requirements are met, but handling damage increases
Solution Approach 1:
The patent integrates multiple temperature chambers within a single test system, allowing components to remain mounted while being tested at different temperatures (e.g., -40°C, 95°C, 125°C) for BI tests, weak cell tests, and speed tests. This eliminates the need to remove and rehandle components between temperature-specific tests.
4Reliability
If expensive product-specific tooling is used for each DRAM package type, then proper electrical connection is achieved, but tooling cost increases
Solution Approach 1:
The test system employs universal test heads with configurable electrical connection mechanisms that can accommodate different DRAM package types (FBGA, LFBGA, WFBGA, etc.) without requiring expensive product-specific tooling. The system can be programmed to recognize and properly connect to various package types, significantly reducing tooling costs while maintaining reliable electrical connections.
Data Source
AI summary
A tester board system that includes a frame upon which a plurality of motherboards can be inserted for the purposes of BI and other types of component testing. Each motherboard has memory channels that can accommodate a plurality of memory components for testing, and the memory channels are connected to a CPU. In preferred embodiments, the CPU is on the underside of the motherboard and the memory channels on the top side of the motherboard.