Multi-Tile Synchronization via Aggregated Exit States
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-tile processing systems face challenges in efficiently synchronizing workloads across multiple tiles, particularly in bulk synchronous parallel (BSP) communication schemes, where each tile must complete a compute phase before proceeding to an exchange phase, leading to increased latency and code density.
Innovation Solution
A processor architecture with a dedicated instruction set that includes a synchronization instruction for validating the result of a group of tiles after all have completed the compute phase, allowing for reduced latency and lower code density by aggregating local exit states into a global exit state register, enabling efficient synchronization and overall outcome determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier synchronization is implemented in multi-tile processing systems, then all tiles can be synchronized to complete compute phases before proceeding to exchange phases, but latency and code density increase
Solution Approach 1:
The patent replaces traditional software-based barrier synchronization mechanisms with dedicated hardware logic circuits. The synchronization logic includes tile completion detectors that monitor compute phase completion status and control signal generators that manage phase transitions. This hardware-based approach eliminates the need for complex software polling and waiting loops, thereby reducing latency while maintaining synchronization correctness across all tiles.
Solution Approach 2:
The patent introduces dedicated synchronization logic as an intermediary component between tiles and the exchange phase. This logic acts as a mediator that receives completion signals from all tiles, validates that all compute phases are complete, and then enables the transition to the exchange phase. This intermediary approach centralizes synchronization control and reduces the burden on individual tiles, lowering overall system latency.
2Adaptability or versatility
If traditional software-based synchronization methods are used, then implementation flexibility is maintained, but code density increases and performance decreases
Solution Approach 1:
The patent substitutes software-based synchronization control with dedicated hardware logic circuits embedded in the processing system. The synchronization logic includes completion detectors and control signal generators that operate in hardware, replacing software polling, waiting loops, and conditional checks. This hardware implementation maintains synchronization flexibility through configurable logic while dramatically improving processing efficiency by eliminating software overhead and enabling parallel operation.
3Reliability
If all tiles synchronize at the same barrier point, then coordination between tiles is achieved, but tiles with different compute completion times cause waiting latency
Solution Approach 1:
The patent implements dynamic synchronization where each tile's completion status is independently detected and tracked by hardware logic. The synchronization logic continuously monitors compute phase completion signals from all tiles and dynamically determines when all tiles have finished. This dynamic approach allows tiles to proceed at different rates during the compute phase without causing waiting latency, as the enable signal for the exchange phase is generated only when all completion signals are received, eliminating the need for slow tiles to wait artificially.
Data Source
AI summary
A processing system comprising multiple tiles and an interconnect between the tiles. The interconnect is used to communicate between a group of some or all of the tiles according to a bulk synchronous parallel scheme, whereby each tile in the group performs an on-tile compute phase followed by an inter-tile exchange phase with the exchange phase being held back until all tiles in the group have completed the compute phase. Each tile in the group has a local exit state upon completion of the compute phase. The instruction set comprises a synchronization instruction for execution by each tile upon completion of its compute phase to signal a sync request to logic in the interconnect. In response to receiving the sync request from all the tiles in the group, the logic releases the next exchange phase and also makes available an aggregated a state of all the tiles in the group.