Multi-Transceiver Signal Generation With FIFO Phase Alignment
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Solution Overview
Problem
Existing signal generation devices using FPGAs struggle to output high-speed serial data with aligned phases from multiple transceivers, leading to unintended data generation and incorrect bit error rate (BER) measurements due to excessive phase differences between channels.
Innovation Solution
A signal generation device and method that includes a parallel data output unit, transceiver unit, and phase synchronization control unit configured on an FPGA, utilizing FIFOs, PISOs, and phase adjustment units to align the phases of serial data output from multiple transceivers to within 0.1 UI, allowing flexible adaptation to changing standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transceivers are used to achieve high-speed serial data output, then the signal output rate is improved, but the phase alignment between channels deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the phase difference detection unit continuously monitors the phase alignment between multiple transceiver channels and feeds this information back to the phase adjustment units. This closed-loop control enables dynamic phase correction, ensuring that high-speed serial data output from multiple transceivers maintains precise phase alignment (within 0.1 UI) despite variations in operating conditions or transceiver characteristics.
2Ease of operation
If individual clock inputs are provided to each transceiver channel for phase adjustment, then the phase control capability is improved, but the IO resource consumption increases
Solution Approach 1:
The patent merges the clock input resources by providing a single common clock signal to all transceiver channels instead of individual clock inputs. The phase adjustment units then internally generate the necessary phase-shifted clock signals for each channel based on this common clock, significantly reducing IO resource consumption while maintaining full phase control capability across all channels.
Solution Approach 2:
The patent introduces an intermediary phase adjustment unit that acts as a mediator between the common clock input and the multiple transceiver channels. This intermediary component generates the required phase-shifted clock signals internally, eliminating the need for multiple external clock inputs while preserving the ability to independently adjust the phase of each channel.
3Measurement precision
If the phase difference between channels is reduced to 0.1 UI or less, then the data accuracy is improved, but the complexity of phase synchronization increases
Solution Approach 1:
The patent implements a self-service mechanism where the phase synchronization system automatically detects and corrects phase differences between channels without requiring external intervention or complex manual calibration. The phase difference detection unit continuously monitors alignment, and the phase adjustment units automatically modify their output to maintain phase coherence, enabling the system to self-correct and maintain high data accuracy (phase difference ≤ 0.1 UI) autonomously.
Data Source
AI summary
A signal generation device includes m transceivers, a usage amount determination unit that executes a usage amount determination process that determines the usage amount of the FIFO of each transceiver, and a phase adjustment unit that adjusts the phase of the read clock signal for the FIFO. The signal generation device performs the second usage amount determination process on the condition that the count that the usage amount of the FIFO of each transceiver is determined to be less than the usage amount threshold by the first usage amount determination process consecutively reaches the first determination count, and terminates the adjustment of the phase of the read clock signal on the condition that the count that the usage amount of the FIFO of each transceiver is determined by the second usage amount determination process to be greater than the usage amount threshold consecutively reaches the second determination count.


