Memory Array with Multi-Transistor Cells for Access Count Tracking
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Solution Overview
Problem
As memory components decrease in size, the increased density of memory cells leads to faster data degradation due to repeated access, known as a 'row hammer' attack, which affects nearby memory cells. Existing solutions require additional time for tracking access counts, degrading memory performance.
Innovation Solution
The integration of both 1T and MT memory cells in a memory array, where MT cells are used for counter memory cells to store access counts, allowing for faster read-modify-write cycles. This is achieved by using same or complementary polarity memory cells, folding bit lines, and rerouting LIO lines, which minimizes layout changes and process differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access count tracking is implemented to prevent row hammer attacks, then memory reliability is improved, but access time increases due to additional write operations
Solution Approach 1:
The patent divides the memory array into two distinct types of memory cells: 1T (single transistor) cells for general data storage and MT (multi-transistor) cells specifically for access count tracking. This segmentation allows each cell type to be optimized for its specific function, with MT cells having dedicated circuitry for faster read-modify-write operations required for access tracking without impacting the performance of regular 1T data cells.
Solution Approach 2:
The patent applies different structural qualities to different regions of the memory array. MT cells used for access tracking have specialized circuitry including access count storage elements and dedicated sense amplifiers, while regular 1T cells maintain their simpler structure for general data storage. This local differentiation enables efficient access tracking in specific locations without degrading the overall memory performance.
2Quantity of substance
If memory cell density is increased by decreasing component size, then storage capacity is improved, but data degradation rate increases due to row hammer attacks
Solution Approach 1:
The patent implements preliminary tracking of access counts using MT cells before data degradation becomes problematic. By continuously monitoring and counting access patterns in real-time, the system can identify rows susceptible to row hammer attacks and apply preventive refresh operations or error correction before data degradation occurs, thus protecting against the harmful effects of high-density memory architecture.
3Productivity
If MT memory cells are integrated into the memory array, then access tracking speed is improved, but layout area increases
Solution Approach 1:
The patent merges the access count storage and update functionality directly into the MT memory cell structure itself, rather than using separate external counters. The MT cells incorporate access count storage elements and dedicated sense amplifiers within the same cell structure, eliminating the need for separate tracking circuitry and reducing the overall layout area while maintaining fast access tracking performance.
Data Source
AI summary
Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.