Multi-trapping Layer Flash Memory Cell Structure
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Solution Overview
Problem
Conventional flash memory cells face challenges in scaling down write/erase voltages due to charge leakage issues, particularly with thin tunneling oxide layers, which affect storage capacity and data retention time.
Innovation Solution
The implementation of a multi-trapping layer (MTL) flash memory cell structure with stacked gates comprising multiple tunneling and storage layers, including a retention layer and composite layers with varying band gaps, to enhance charge storage and retention while reducing leakage, allowing for efficient programming and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the thickness of the tunneling oxide layer is decreased to scale down write/erase voltages, then write/erase voltages are reduced, but charge leakage increases significantly
Solution Approach 1:
The single tunneling oxide layer is segmented into multiple tunneling layers (first tunneling layer and second tunneling layer) separated by storage layers. This segmentation allows each tunneling layer to be thinner with lower individual barriers, reducing write/erase voltages while the cumulative structure maintains charge retention by preventing leakage paths.
Solution Approach 2:
The patent implements a nested structure where storage layers (containing trapped charges) are positioned between tunneling layers. The first storage layer is nested between the control gate and the second tunneling layer, while the second storage layer is nested between the second tunneling layer and the substrate. This nesting configuration allows charges to be stored in discrete regions, preventing leakage through thin oxide layers while enabling efficient programming and erasing operations.
2Quantity of substance
If a conventional SONOS structure with silicon nitride storage layer is used, then charge storage is achieved, but data retention time is reduced due to high conduction band discontinuity
Solution Approach 1:
The patent changes the material parameters of the storage layers by using materials with different conduction band offsets relative to silicon (such as oxynitride, carbon-rich oxide, or aluminum oxide) instead of conventional silicon nitride. This parameter change in conduction band alignment reduces the discontinuity barrier, allowing trapped charges to remain stable for longer periods while maintaining efficient charge injection during programming operations.
Solution Approach 2:
The patent employs composite material structures where storage layers are formed from materials combining oxide and nitride characteristics (oxynitride) or other dielectric materials with tailored electrical properties. These composite materials provide optimized conduction band offsets that balance charge trapping efficiency with long-term charge retention, overcoming the limitations of single-material storage layers.
3Quantity of substance
If multiple storage layers are stacked to increase storage capacity beyond four bits, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent implements a universal stacked gate structure where identical or similar first and second tunneling layer/storage layer pairs can store multiple bits of data independently. Each tunneling layer/storage layer combination functions as an independent storage unit that can be programmed and erased separately, allowing the same structural motif to be replicated for increasing storage capacity without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent transitions from planar storage to vertical stacking, adding the vertical dimension to the memory structure. By stacking tunneling and storage layers in the vertical direction rather than expanding horizontally, the patent achieves increased storage capacity within the same footprint while maintaining a structured approach that manages complexity through vertical integration rather than horizontal expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MTL flash memory cell achieves increased storage capacity, improved data retention time, and reduced write/erase voltages by utilizing multiple tunneling and storage layers with adjusted band gaps, enabling efficient multi-bit programming and self-limiting operations.
Implementation Method 1
Each of the tunneling layers has a band gap no smaller than band gaps of underlying tunneling layers, and at least one tunneling layer has a greater band gap than band gaps of the underlying tunneling layers
Implementation Method 2
A first storage layer and a second storage layer are alternately stacked on the substrate... Each of the at least two composite layers comprises a tunneling layer and a storage layer on the tunneling layer
Implementation Method 3
The semiconductor device further includes a blocking layer adjoining the first storage layer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a top gate over the semiconductor substrate, and a stacked gate between the top gate and the semiconductor substrate. The stacked gate includes a first tunneling layer, a first storage layer adjoining the first tunneling layer, and an additional layer adjoining the first tunneling layer. The additional layer is selected from the group consisting of a retention layer and an additional composite layer. The additional composite layer comprises a second tunneling layer and a second storage layer adjoining the second tunneling layer. The semiconductor device further includes a blocking layer adjoining the first storage layer.