Multi-Type Spacer Etching for Metal Gate Formation
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Solution Overview
Problem
The manufacturing of high-k metal gate (HKMG) semiconductor devices faces challenges in minimizing oxygen diffusion and removing polysilicon dummy gates due to the obstruction caused by silicon nitride spacers, leading to undesirable trapezoidal profiles and voids in the metal gate member, which affects the quality and yield of the semiconductor device.
Innovation Solution
A method involving the formation of multiple layers of spacers with different etch rates using stress proximity technique (SPT) wet etch, specifically using phosphoric acid at 115° C, to selectively remove spacers and polysilicon dummy gates, ensuring effective protection of work function layers and metal gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride spacers are used to minimize oxygen diffusion, then oxygen diffusion is minimized, but the removal of polysilicon dummy gate is obstructed and trapezoidal profile is formed
Solution Approach 1:
The spacer structure is segmented into three types with different etch rates. First-type spacers (closest to dummy gate) have lowest etch rate to protect dummy gate, second-type spacers have intermediate etch rate, and third-type spacers (outermost) have highest etch rate for easy removal. This segmentation allows selective removal of spacers while preserving the dummy gate structure.
Solution Approach 2:
Different regions of the spacer structure are assigned different local qualities through varying etch rates. The first-type spacers maintain low etch rate properties to protect the dummy gate, while third-type spacers have high etch rate properties for easy removal. This local differentiation resolves the contradiction between protection and removal ease.
2Reliability
If silicon nitride spacers are used to minimize oxygen diffusion, then oxygen diffusion is minimized, but undesirable trapezoidal profile of metal gate space is formed
Solution Approach 1:
The spacer system is divided into three segments with progressively increasing etch rates from inner to outer spacers. This segmentation enables controlled removal where outer spacers are removed first to create vertical walls, while inner spacers remain to define the final metal gate space geometry, preventing trapezoidal profile formation.
Solution Approach 2:
The multi-type spacer structure performs preliminary actions in a specific sequence: third-type spacers are removed first to establish vertical boundaries, then second-type spacers are partially removed, leaving first-type spacers to define the final metal gate space. This preliminary structured removal prevents undesirable profile formation before metal gate filling.
3Device complexity
If conventional single-type spacers are used, then manufacturing process is simple, but voids are formed in metal gate member
Solution Approach 1:
The spacer structure is segmented into three types with distinct etch rates, where first-type spacers protect the dummy gate and define the metal gate space, while second and third-type spacers are selectively removed. This segmentation prevents void formation by ensuring proper space definition and metal gate material filling, outweighing the increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the satisfactory quality and performance of work function layers and metal gate members by maintaining desirable structures and minimizing voids, thereby enhancing the overall quality and yield of semiconductor devices.
Implementation Method 1
The etch may be stress proximity technique (SPT) wet etch. The etch may be performed using a phosphoric acid (H3PO4). The etch may be performed at a temperature of 115° C. The first-type spacers may have a first etch rate in the etch. The second-type spacers may have a second etch rate in the etch. The third-type spacers may have a third etch rate in the etch.
Data Source
AI summary
A method for manufacturing a semiconductor device may include forming a gate structure that includes a dummy gate member on a substrate. The method may further include forming two first-type spacers such that the dummy gate member is positioned between the first-type spacers. The method may further include forming two second-type spacers such that the first-type spacers are positioned between the second-type spacers. The method may further include forming two third-type spacers such that the second-type spacers are positioned between the third-type spacers. The method may further include performing etch to remove the third-type spacers and to at least partially remove the second-type spacers. The method may further include removing at least a portion of the dummy gate member to form a space between remaining portions of the first-type spacers. The method may further include providing a metal material in the space for forming a metal gate member.