Multi-Unit Chip Layout Without Scribe Lines for Higher Functional Density

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Solution Overview

Problem

The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining manufacturing efficiency and reducing costs, as the complexity of processing and manufacturing increases with smaller geometries and more complex circuits.

Innovation Solution

The solution involves a chip with a substrate and multiple functional units, each with its own set of pads, including I/O, power, and ground pads, and a central management unit to store statuses, where chiplets are bonded to normal functional units using Cu—Cu bonding, allowing for efficient communication and management without scribe lines, and accommodating different sizes and types of units like memory and core units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of functional units and pads is increased to increase functional density, then productivity and functional density are improved, but device complexity and manufacturing complexity increase

Engineering Contradiction:
Improvefunctional densityVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The chip is divided into multiple independent functional units, each with its own set of pads. This segmentation allows each unit to be independently tested, packaged, and managed, reducing the overall complexity of processing and manufacturing while increasing functional density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional planar chip design to a three-dimensional stacked architecture where chiplets are bonded vertically on functional units. This dimensional change increases functional density without proportionally increasing planar manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If scaling down geometry size is implemented to increase production efficiency, then productivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveproduction efficiencyVSAvoidgeometry precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

By segmenting the chip into standardized functional units with uniform pad configurations, the patent enables modular manufacturing where precision requirements are distributed across identical repeating units rather than requiring high precision across the entire complex circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates universal functional units that can be replicated and stacked multiple times. This universality allows standardized manufacturing processes to be applied repeatedly, maintaining precision requirements while increasing overall production efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiple functional units with independent pads are implemented, then functional density and adaptability are improved, but device complexity increases

Engineering Contradiction:
Improvefunctional unit configurationVSAvoidpad management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Each functional unit is segmented with its own dedicated pads, creating independent interfaces that simplify pad management. The central management unit tracks pad assignments systematically, transforming complexity into organized modularity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The central management unit maintains real-time status information of all functional units and pads, providing feedback control for pad assignment and configuration. This systematic management reduces complexity through centralized coordination and tracking.

Inventive Principle:
Principle #23Feedback

4Strength

If chiplets are bonded on functional units using Cu-Cu bonding, then joining strength and electrical conductivity are improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvebonding strengthVSAvoidbonding alignment precision
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent uses homogeneous Cu-Cu bonding materials and processes for all chiplet-to-functional-unit connections. This uniformity simplifies the bonding process and reduces precision requirements compared to using multiple different bonding technologies.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

By dividing the chip into modular functional units with standardized pad layouts, the patent enables repetitive bonding operations with fixed alignment references, reducing the cumulative precision requirements compared to monolithic chip design.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables increased functional density and efficiency by eliminating scribe lines, allowing for independent operation of functional units, efficient bonding, and effective management of both normal and failed units, thereby enhancing production efficiency and reducing costs.

Implementation Method 1

The chiplets are bonded on the normal functional units by a Cu—Cu bonding process

Methodology Applied
Scientific EffectCu-Cu bonding: Diffusion Welding

Data Source

PatentUS11894356B2Chip having multiple functional units and semiconductor structure using the same
Publication Date: 2024.02.06 MACRONIX INTERNATIONAL CO LTD
  • US11894356B2 patent drawing
  • US11894356B2 patent drawing
  • US11894356B2 patent drawing

AI summary

A chip includes a substrate and a plurality of functional units on the substrate, in which each of the functional units has its own set of pads. The functional units are physically connected and there is no scribe line passes through the chip. A semiconductor structure having the chip is also disclosed.