Multi-unit Wiring Structure for Semiconductor Substrate Warpage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of I/O connections in semiconductor chips leads to warpage issues in packaging substrates, affecting the yield of semiconductor device packages due to the need for larger substrates with more dielectric layers, which results in higher manufacturing costs and lower yield rates.
Innovation Solution
A wiring structure and manufacturing method involving a multi-layer substrate with redistribution layers and insulation walls, where units with circuit and dielectric layers are stacked and encapsulated, reducing the number of dielectric layers and improving yield while maintaining cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the substrate size is increased to accommodate more I/O connections, then the number of I/O connections is improved, but warpage of the semiconductor chip package becomes more severe
Solution Approach 1:
The substrate is divided into multiple units (first units, second units, third units) arranged in a multi-layer structure. Each unit contains circuit layers and dielectric layers, and they are connected through redistribution layers. This segmentation allows the substrate to accommodate more I/O connections without requiring a single large substrate, thereby reducing warpage.
Solution Approach 2:
The patent transitions from a two-dimensional substrate layout to a three-dimensional multi-layer structure. Units are stacked vertically with redistribution layers connecting corresponding circuits between layers. This vertical arrangement enables more I/O connections to be implemented without increasing the horizontal substrate area, thus avoiding warpage issues associated with larger substrates.
2Quantity of substance
If the number of dielectric layers is increased to support more I/O connections, then the I/O capacity is improved, but manufacturing cost increases and yield rate decreases
Solution Approach 1:
Instead of adding more dielectric layers within a single unit, the patent segments the substrate into multiple units distributed across different layers. Each unit has a manageable number of dielectric layers, but the overall I/O capacity is achieved through the multi-unit, multi-layer configuration. This approach reduces manufacturing complexity and improves yield rate while maintaining high I/O capacity.
Solution Approach 2:
Multiple units are combined in a multi-layer stack with redistribution layers connecting them. This merging of units across layers achieves the equivalent of having many more I/O connections without requiring a corresponding increase in dielectric layers within each unit, thereby reducing manufacturing cost and improving yield.
Data Source
AI summary
A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.