Multi-Uplink PCIe Device Enumeration via DVSEC Registers
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Solution Overview
Problem
In multi-socket computing systems, the increased bandwidth demand due to higher processing power leads to bandwidth pressure across processor interconnects, resulting in decreased system performance, and a single PCIe port is often insufficient to meet the bandwidth requirements, potentially causing reliability and accessibility issues.
Innovation Solution
Implementing a multi-uplink PCIe device with a Designated Vendor-Specific Extended Capability (DVSEC) structure that allows for multiple communication links between the device and processors, enabling each port to connect to a different socket, thereby distributing traffic and reducing cross-socket interconnect pressure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If processing power is increased in multi-socket systems, then computing capability is improved, but bandwidth pressure on processor interconnects increases resulting in decreased system performance
Solution Approach 1:
The device is divided into multiple independent communication links (first link, second link, etc.), each connecting to different sockets. This segmentation allows traffic to be distributed across multiple interconnect paths, preventing any single interconnect from becoming a bandwidth bottleneck while maintaining high computing capability.
2Device complexity
If a single PCIe port is used, then device simplicity is maintained, but bandwidth requirements cannot be met causing reliability issues
Solution Approach 1:
The device incorporates multiple PCIe ports (first PCIe port, second PCIe port, etc.) that can independently communicate with different sockets. This multi-functionality enables the device to meet high bandwidth requirements by utilizing multiple communication paths simultaneously, while each individual port maintains standard PCIe specifications for compatibility.
3Reliability
If multiple communication links are implemented, then bandwidth pressure is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces capability registers as intermediaries that automatically manage the complexity of multiple communication links. These registers store configuration information (link association, port identifiers, total port count) and enable software to automatically discover and configure the multi-link device, reducing the perceived complexity for system integrators.
4Ease of operation
If capability registers with detailed fields are implemented, then device enumeration and configuration is improved, but register structure complexity increases
Solution Approach 1:
The capability registers are designed to be self-descriptive, containing all necessary information (link association fields, port identifier fields, total port count fields) that enables software to automatically enumerate and configure the device without external assistance. The registers serve themselves by providing complete configuration data that software can parse and act upon autonomously.
Data Source
AI summary
A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.