Multi-Version Library Cells for Dense Metal-Gate IC Layouts
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling multi-gate transistors to 10 nm or sub-10 nm technology nodes due to variability and constraints, limiting the integration of new technologies or methodologies required for future nodes.
Innovation Solution
Implementing a multi version library cell handling approach where gate lines and metal 1 lines are misaligned, with two standard cell versions available for each cell, allowing increased density and alignment at the block level, and using spacer mask patterning to achieve tighter pitch grating structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nm or sub-10 nm technology nodes due to process variability
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned double patterning, self-aligned quadruple patterning) where each step creates a portion of the final pattern. This segmentation allows achievement of sub-10 nm precision by breaking down the complex patterning task into manageable steps, each with relaxed individual requirements but cumulative high precision.
Solution Approach 2:
Mandrel structures and spacer layers are formed in advance before the final active pattern is created. These preliminary structures serve as templates that guide subsequent patterning steps, ensuring precise alignment and dimensions are achieved before the actual transistor gates and interconnects are formed.
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The self-aligned patterning methodology uses the previously formed structures (mandrels, spacers) to automatically define the positions of subsequent features without requiring additional alignment steps. The spacer width, controlled by conformal deposition thickness, directly determines the final feature pitch, making the process self-correcting and highly precise even at reduced feature sizes.
Solution Approach 2:
The patent controls critical dimensions by adjusting deposition parameters (film thickness, conformality) and etch parameters rather than relying solely on lithographic resolution. By changing these process parameters, precise feature sizes and spacing are achieved regardless of the reduced feature dimensions, maintaining manufacturing precision while increasing device density.
3Productivity
If multi-gate transistors are scaled to increase capacity, then productivity is improved, but manufacturing precision deteriorates due to overwhelming process constraints
Solution Approach 1:
The complex multi-gate transistor structure is fabricated through segmented patterning steps where each gate, source, and drain region is defined by separate self-aligned processes. This allows precise control over the three-dimensional geometry of multi-gate devices while maintaining compatibility with existing fabrication infrastructure, enabling high integration capacity without sacrificing precision.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional self-aligned patterning using vertical spacer structures. This dimensional change allows precise control of horizontal feature spacing through vertical film thickness control, enabling accurate fabrication of scaled multi-gate transistors with multiple gates surrounding the channel in three dimensions.
4Area of stationary object
If metal 1 lines are aligned with gate lines, then manufacturing simplicity is maintained, but area is wasted due to inability to increase pitch density
Solution Approach 1:
The patent deliberately creates asymmetric relationships between metal 1 line positions and gate line positions. By offsetting these features and using self-aligned spacer formation, the design achieves higher pitch density for metal interconnects compared to the gate layer, maximizing area utilization while the asymmetric layout is managed through automated placement tools that select from multiple cell versions.
Solution Approach 2:
The methodology provides dynamic flexibility by offering multiple versions of standard cells (e.g., even/odd poly pitch versions) that can be selectively placed during automated physical design. This dynamic selection allows the layout to adapt to different pitch requirements in different regions of the chip, maximizing overall area utilization while managing layout complexity through automation.
5Adaptability or versatility
If standard cell versions are increased to accommodate pitch variations, then adaptability is improved, but device complexity increases
Solution Approach 1:
Multiple versions of the same standard cell type (e.g., inverter, NAND, NOR) are created with different interconnect pitch configurations but identical functional behavior. These universal cell versions can be placed in different locations throughout the design to accommodate varying pitch requirements, providing adaptability while maintaining functional consistency. The cell library is organized to allow automated tools to select the appropriate version based on local pitch constraints.
Data Source
AI summary
Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.