Multi-Voltage Buffer Circuit with Switched PMOS Output Path

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Solution Overview

Problem

PMOS transistors in tolerant buffer circuits face challenges in simultaneously meeting the requirements of having a breakdown voltage for the VDDH level and being gate-controlled with the VDDL level, leading to insufficient output signal generation at different voltage levels.

Innovation Solution

Incorporating a switch circuit controlled by a high voltage level, allowing the backgate of PMOS transistors to be fed with a lower voltage, enabling stable operation and output of multiple high voltage levels, while using transistors with lower breakdown voltages that can be gate-controlled with the VDDL level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the PMOS transistor is designed to have a breakdown voltage for the VDDH level, then it can operate with high voltage, but it cannot be gate-controlled with the VDDL level

Engineering Contradiction:

Improvebreakdown voltageVSAvoidgate control capability

Core Design Contradiction:

StrengthVSEase of operation

Solution Approach 1:

The patent divides the PMOS transistor control into two separate transistors: a first PMOS transistor (M109) controlled by VDDL for low-voltage operation, and a second PMOS transistor (M111) controlled by VDDH for high-voltage operation. This segmentation allows each transistor to be optimized for its specific voltage range, resolving the contradiction between high breakdown voltage requirement and low-voltage gate control capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a level shifter circuit (P7) as an intermediary that converts the VDDL control signal to a VDDH-level control signal. This intermediary enables the second PMOS transistor to be properly controlled at high voltage levels while the first PMOS transistor continues to respond to VDDL signals, thus resolving the gate control limitation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If the PMOS transistor cannot be gate-controlled with the VDDL level, then it cannot turn ON at low voltage, but using a transistor with lower breakdown voltage prevents operation at high voltage levels

Engineering Contradiction:

Improvegate control with VDDLVSAvoidbreakdown voltage

Core Design Contradiction:

Ease of operationVSStrength

Solution Approach 1:

The patent segments the high-voltage output path into two separate PMOS transistors: M109 with lower breakdown voltage that responds to VDDL gate control, and M111 with higher breakdown voltage that responds to VDDH gate control. This segmentation allows the system to achieve both low-voltage gate controllability and high-voltage operation capability simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic voltage level switching by using control signals that can operate at different voltage levels. The first PMOS transistor operates dynamically at VDDL level for normal control, while the second PMOS transistor is activated at VDDH level when high-voltage output is required, enabling adaptive operation across different voltage conditions.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If a single PMOS transistor is used for both VDDL and VDDH level control, then the circuit is simple, but it cannot simultaneously fulfill both voltage level requirements

Engineering Contradiction:

Improvetransistor configurationVSAvoidmulti-voltage level output capability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments the single PMOS transistor into two separate transistors (M109 and M111) with different breakdown voltage characteristics. M109 handles VDDL-level control signals while M111 handles VDDH-level control signals. This segmentation increases device complexity slightly but enables the circuit to output multiple high voltage levels, thus resolving the contradiction between simplicity and versatility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a universal buffer circuit that can output multiple voltage levels (both VDDL and VDDH) through the coordinated operation of two PMOS transistors. The first transistor provides universality for low-voltage operation while the second transistor adds high-voltage capability, making the circuit adaptable to various voltage level requirements without needing separate circuits for each voltage level.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8008952B2Buffer circuit having switch circuit capable of outputing two and more different high voltage potentials

Publication Date: 2011.08.30 RENESAS ELECTRONICS CORP

AI summary

A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages. The buffer includes a logic control circuit, a first MOS transistor provided between a power supply for feeding the first high voltage and an output terminal, the first MOS transistor including a gate receiving a control signal of the first high voltage level outputted from the logic control circuit, and a backgate receiving the first high voltage, a second MOS transistor provided between a power supply for feeding the second high voltage and the output terminal, the second MOS transistor including a gate receiving a control signal of the second high voltage level outputted from the logic control circuit, and a backgate receiving the second high voltage, and a first switch circuit provided between the first MOS transistor and the output terminal and controlled ON/OFF state thereof by the control signal of the second high voltage level.