Multi-Voltage DAC ADC With Mismatch Error Shaping
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Solution Overview
Problem
Conventional signal processing chip designs for multi-channel applications face challenges in reducing chip area due to the need for multiple analog-to-digital converters (ADCs) and large anti-aliasing filters, which increase the chip size and power consumption.
Innovation Solution
A signal processing system employing an analog-to-digital converter (ADC) with digital-to-analog converter (DAC) circuits operating in different voltage domains, utilizing a mismatch error shaping (MES) technique to mitigate mismatch errors and reduce chip area by injecting an analog injection value to convert analog signals, thereby allowing for shared ADC usage across channels without the need for large anti-aliasing filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple ADCs are implemented in a single chip for multi-channel applications, then the signal processing capability for different channels is improved, but the chip area increases inevitably
Solution Approach 1:
The patent merges multiple ADC functionalities into a single ADC by implementing a time-multiplexing architecture where one ADC serves multiple channels sequentially. The ADC is shared between different channels through time-division multiplexing, eliminating the need for multiple separate ADC circuits and thereby reducing chip area while maintaining multi-channel processing capability.
Solution Approach 2:
The single ADC is designed to perform multiple functions by serving different channels at different time intervals. The ADC structure incorporates universal components that can handle various channel inputs, making it a multi-functional device that replaces what would traditionally require multiple dedicated ADCs.
2Measurement precision
If a time-multiplexing ADC is implemented by a delta-sigma ADC, then the ADC resolution is improved, but large-sized anti-aliasing filters are needed by each channel to ensure signal quality
Solution Approach 1:
The patent extracts the anti-aliasing filtering function from individual channel requirements and implements a shared anti-aliasing filter that serves all channels through the time-multiplexing architecture. Since channels are processed sequentially, a single filter can be reused for each channel during its active time slot, eliminating the need for multiple large-sized filters and significantly reducing the required filter area.
Solution Approach 2:
The system employs periodic switching between channels, where the anti-aliasing filter is activated for each channel in sequence during its designated time slot. This periodic operation allows the same filter to be reused across multiple channels, reducing the total filter area required compared to having dedicated filters for each channel.
3Area of stationary object
If a time-multiplexing ADC is used, then the chip area is reduced, but the effective sampling frequency is reduced due to intermittent reset intervals
Solution Approach 1:
The patent implements preliminary reset operations that are efficiently managed during channel transitions. By preparing and resetting the ADC and CIC filter in advance during idle periods or through optimized reset sequencing, the system minimizes the impact of reset intervals on the overall sampling frequency, maintaining higher effective sampling rates despite the time-multiplexed operation.
Data Source
AI summary
A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.