Multi-Voltage Transistor Gate Oxide Integration Without Acid Over-Etch
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Solution Overview
Problem
Existing fabrication methods for high-voltage integrated circuits face issues with over-etching of low-voltage device isolation and fluctuations in high-voltage gate oxide thickness due to the use of large amounts of acid, affecting electrical properties and reliability.
Innovation Solution
A fabrication method that forms a high-voltage transistor, medium-voltage transistor, and low-voltage transistor on the same silicon substrate, using a hard mask layer to protect the high-voltage and low-voltage areas during medium-voltage gate oxide growth, avoiding additional growth of the gate oxide layer above these areas and controlling the etching process to maintain precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large amount of acid is used to remove gate oxide layer of medium-voltage device, then the gate oxide can be completely removed, but the shallow trench isolation oxide is over-etched and the high-voltage gate oxide thickness fluctuates
Solution Approach 1:
The patent divides the substrate into distinct voltage regions (low-voltage, medium-voltage, high-voltage) and applies region-specific protection strategies. The shallow trench isolation oxide in low-voltage areas and high-voltage gate oxide are selectively protected from acid etching through precise photolithography masking, allowing complete removal of medium-voltage gate oxide while preserving other oxides.
Solution Approach 2:
The patent introduces photolithography masks as intermediary protective layers that selectively block acid from reaching sensitive oxide regions. The masks are precisely patterned to cover only the areas requiring protection (low-voltage STI and high-voltage gate oxide) while leaving medium-voltage gate oxide exposed for complete removal.
2Manufacturing precision
If gate oxide thickness of medium-voltage device is several hundred angstroms, then sufficient insulation is achieved, but large amount of acid is required for removal which affects other areas
Solution Approach 1:
Photolithography masks serve as intermediary protective barriers that allow complete removal of thick medium-voltage gate oxide (several hundred angstroms) while preventing acid from reaching adjacent sensitive structures. The masks are precisely positioned to cover only non-target areas during the etching process.
Solution Approach 2:
The patent applies different protection strategies to different regions: low-voltage areas receive protection for STI oxide, high-voltage areas receive protection for gate oxide, while medium-voltage areas are left unprotected for complete gate oxide removal. This localized quality control enables selective etching based on regional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents deterioration of the step height and electrical reliability of low-voltage devices, reduces fluctuations in high-voltage gate oxide thickness, and enhances process control, making it suitable for mass production.
Implementation Method 1
firstly, grow a high-voltage area gate oxide layer in a thermal oxidation manner
Implementation Method 2
growing a medium-voltage gate oxide layer in a manner of first an ISSG (In-Situ Steam Generation) process
Implementation Method 3
then an HTO (High Temperature Oxidation) process, and growing a gate oxide layer required by the medium-voltage device on the surface of the whole wafer
Data Source
AI summary
The present application discloses a fabrication method for an integrated structure of transistors with different operating voltages. A high-voltage transistor area and a low-voltage transistor area are protected by a retained hard mask layer before a medium-voltage gate oxide layer is grown, so as to avoid additional growth of gate oxide layers above active areas of the high-voltage transistor area and the low-voltage transistor area, thereby avoiding the deterioration of a step height of the low-voltage transistor area due to the subsequent use of a large amount of acid to remove the gate oxide layer additionally grown above the active area of the low-voltage transistor area, and preventing the electrical property and the reliability of a low-voltage device from being subsequently influenced while avoiding the influence of the etching with the large amount of acid on the thickness of a high-voltage gate oxide layer which has already been grown.