Multi-Voltage I/O Cell Safe-State Configuration
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Solution Overview
Problem
Integrated circuit system-on-chips (SoCs) face challenges in configuring general purpose input/output (GPIO) cells before the supply voltage reaches a detection threshold, leading to potential damage due to non-determinant states during power ramp-up, and existing solutions either require additional dedicated pads or complex power sequencing with specialized regulators.
Innovation Solution
A system comprising a first I/O cell, a logic cell, and a trigger signal generation circuit that sets the GPIO cell into a safe-state mode by generating trigger signals based on predetermined voltage thresholds, eliminating the need for dedicated pads and specialized regulators by configuring the GPIO cell before the input supply voltage reaches the detection threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a generic power supply ramp-up sequence is used where higher voltage ramps up faster, then the output interface voltage reaches peak value before the input interface voltage reaches detection threshold, but the GPIO cell enters a non-determinant state and may be damaged
Solution Approach 1:
The patent applies preliminary action by configuring the GPIO cell to a safe-state mode before the input interface voltage reaches the detection threshold. The logic circuit detects when the output interface voltage has reached its peak value and proactively sets the voltage selection pins to configure the GPIO cell, ensuring the cell is properly configured before the input voltage becomes active. This prevents the non-determinant state by performing the configuration action in advance.
2Reliability
If dedicated SoC pads are implemented to sample binary values directly to voltage selection pins, then GPIO cells can be configured before input voltage reaches threshold, but area and cost of the SoC increases
Solution Approach 1:
The patent merges the configuration function with existing internal logic circuits and voltage detection mechanisms within the SoC. Instead of adding dedicated external pads and separate configuration circuits, the invention utilizes the existing power supply ramp-up detection logic and integrates the configuration control within the same logic circuit that monitors voltage levels. This consolidation achieves reliable GPIO cell configuration without requiring additional dedicated pads or external components.
3Reliability
If specialized power regulators are implemented to enforce specific power supply ramp-up sequence, then GPIO cells can be configured before input voltage reaches threshold, but cost and design complexity increases
Solution Approach 1:
The patent implements self-service by using the existing power supply ramp-up characteristics and internal voltage detection capabilities of the SoC to automatically control the GPIO cell configuration. The logic circuit monitors the output interface voltage and autonomously determines when to configure the GPIO cell based on the natural ramp-up sequence. This eliminates the need for specialized power regulators with complex control circuits, as the system uses its own existing resources to achieve proper configuration timing.
Data Source
AI summary
An integrated circuit (IC) includes a first I/O cell, a logic cell, a trigger signal generation circuit, and a second I/O cell having a voltage selection pin. I/O interfaces of the first I/O cell receive first and second supply voltages, respectively, and I/O interfaces of the second I/O cell receive third and fourth supply voltages, respectively. The first I/O cell generates a first trigger signal when the first supply voltage reaches a first predetermined voltage. The logic cell receives the first trigger signal and generates a safe-state signal. The trigger signal generation circuit generates a second trigger signal when the third supply voltage reaches a second predetermined voltage. The voltage selection pin receives the safe-state signal and the second trigger signal and sets the second I/O cell in a safe-state mode, which protects the second I/O cell from over voltage damage.