Multi-Voltage Power Bus Layout for Low-Drop IC Routing
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Solution Overview
Problem
As computing devices increase in functionality and shrink in size, efficiently delivering supply voltages to load circuits becomes challenging due to the consumption of valuable top-most metal layer tracks by power buses, leading to reduced routing efficiency and increased voltage drops.
Innovation Solution
The implementation of a method where first and second power buses, powered at different supply voltages, extend in a specific direction within defined ranges, with the second power buses positioned between the first power buses, optimizing track usage and reducing voltage drops by breaking up power bus routing and inserting additional power buses to improve power routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power buses are routed in the top-most metal layer to provide lowest resistance routing, then voltage delivery efficiency is improved, but valuable tracks of the top-most metal layer are consumed and not available for other uses
Solution Approach 1:
The patent transitions from two-dimensional routing in the top-most metal layer to three-dimensional routing by utilizing multiple metal layers. Power buses are distributed across different metal layers (first metal layer, second metal layer, third metal layer) with vertical connections via contacts and vias, thereby maintaining low resistance while preserving track availability in each individual layer for other signal routing purposes.
Solution Approach 2:
The patent segments the power bus routing into multiple discrete metal layers rather than concentrating all power routing in a single top-most layer. Each metal layer contains a subset of power buses, and the segmentation allows parallel power delivery paths while freeing up tracks in each layer for signal routing, thus resolving the conflict between power delivery efficiency and routing versatility.
2Area of stationary object
If computing devices shrink in physical dimension to reduce size, then device compactness is improved, but efficient delivery of supply voltages to load circuits becomes increasingly challenging
Solution Approach 1:
The patent employs three-dimensional power bus architecture utilizing multiple stacked metal layers with vertical interconnects (contacts and vias) to deliver power efficiently in compact devices. This vertical dimension enables short power delivery paths that are insensitive to horizontal distance, allowing efficient voltage delivery even when devices are shrunk to small footprints.
Solution Approach 2:
The patent implements a nested power delivery structure where power buses in different metal layers are vertically aligned and connected through contacts and vias, creating a nested configuration. This nesting enables compact power distribution by stacking power paths vertically rather than spreading them horizontally, thus maintaining efficient voltage delivery in reduced device areas.
Data Source
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AI summary
Methods and apparatuses for efficiently providing supply voltages to a load circuit are provided. The apparatus includes a first plurality of first power buses extending in a first direction and within a first range. The first range extends in a second direction. A second plurality of first power buses extends in the first direction and within the first range. The first plurality of first power buses and the second plurality of first power buses are powered at a first supply voltage. A plurality of second power buses extends in the first direction within the first range and a second range. The second range extends in the first direction. The plurality of second power buses is powered at a second supply voltage. The first plurality of first power buses, the second plurality of first power buses, and the plurality of second power buses are in a conductive layer.