Multi-Voltage Semiconductor Layout for Leakage and Breakdown Control
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Solution Overview
Problem
Current semiconductor processing faces challenges in integrating high-voltage, medium-voltage, and low-voltage devices due to issues such as current leakage and control of breakdown voltage as device scales continue to decrease.
Innovation Solution
A method for fabricating a semiconductor device involves providing a substrate with defined high-voltage, medium-voltage, and low-voltage regions, forming specific transistor structures on each region, including fin-shaped structures for low-voltage devices, to achieve controlled voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-voltage devices and FinFET devices are integrated on the same chip, then power switching efficiency is improved and energy loss is reduced, but current leakage increases and breakdown voltage control becomes difficult
Solution Approach 1:
The substrate is divided into distinct high-voltage regions and low-voltage regions, with HV devices and FinFET devices fabricated in separate areas. This spatial segmentation allows each device type to operate at its optimal voltage level without interference, preventing current leakage while maintaining energy efficiency benefits of integration.
Solution Approach 2:
Different structural configurations are applied to different regions: planar structures for high-voltage devices and three-dimensional FinFET structures for low-voltage devices. This local quality approach enables each region to have the specific structural characteristics needed for its voltage level, controlling breakdown voltage while reducing energy loss.
2Productivity
If device scale is decreased to improve integration density, then more devices can be integrated on a single chip, but current leakage increases and breakdown voltage control becomes more difficult
Solution Approach 1:
The chip is segmented into multiple voltage regions (HV, MV, LV) that can be independently designed and optimized. This allows high integration density through compact low-voltage FinFET regions while maintaining proper breakdown voltage control in high-voltage regions through appropriate device sizing and spacing.
Solution Approach 2:
Three-dimensional FinFET structures are employed in low-voltage regions to achieve higher integration density by utilizing vertical channel architecture. This dimensional change allows more devices to be packed into the same area without compromising the breakdown voltage control in high-voltage planar regions.
3Productivity
If three-dimensional FinFET structures are used instead of planar MOS transistors, then channel control is improved and current capacity is increased, but manufacturing complexity increases
Solution Approach 1:
Three-dimensional FinFET structures are selectively implemented only in low-voltage regions where high current capacity is needed, while high-voltage regions maintain simpler planar structures. This local application of complexity achieves the desired current enhancement without unnecessarily complicating the entire device structure.
Solution Approach 2:
The transistor structures are segmented by voltage region, with FinFETs used for low-voltage high-current applications and planar MOS for high-voltage applications. This segmentation allows the system to benefit from FinFET current capacity where needed while avoiding the manufacturing complexity in regions where it is not required.
Data Source
AI summary
A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.