Multi-Voltage Transistor Structure With Aligned Gate and Fin Dimensions
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Solution Overview
Problem
Existing semiconductor technologies face challenges in integrating high voltage, middle voltage, and low voltage transistors on a single chip while maintaining uniform performance and consistent transistor dimensions.
Innovation Solution
A fabricating method that includes forming a substrate with distinct high, middle, and low voltage regions, using trench isolations and gate dielectric layers to create uniform fin structures and gate structures across different voltage transistors, ensuring aligned and consistent transistor dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple voltage transistors are integrated on a single chip, then chip functionality is improved, but manufacturing precision deteriorates due to varying transistor dimension requirements
Solution Approach 1:
The chip is divided into multiple isolation regions (first isolation region, second isolation region, third isolation region) corresponding to different voltage transistors. Each region is independently isolated using deep trench isolation structures, allowing different transistor types to be fabricated in separate zones with region-specific process parameters, thus maintaining dimension precision while enabling multi-functionality
Solution Approach 2:
Different gate dielectric layer thicknesses are used in different isolation regions: a first gate dielectric layer with first thickness for high voltage transistors, a second gate dielectric layer with second thickness for middle voltage transistors, and a third gate dielectric layer with third thickness for low voltage transistors. This local differentiation allows each transistor type to have optimized dimensions suitable for its voltage requirements while maintaining overall manufacturing precision
2Adaptability or versatility
If transistors with different voltage ranges are integrated, then device versatility is improved, but device complexity increases due to multiple gate dielectric layers
Solution Approach 1:
The gate dielectric structure is segmented into multiple independently formed layers: first gate dielectric layer for high voltage transistors, second gate dielectric layer for middle voltage transistors, and third gate dielectric layer for low voltage transistors. Each layer is formed in its respective isolation region with specific thickness and material properties, allowing versatile voltage coverage while managing complexity through spatial separation
Solution Approach 2:
Different physical parameters are applied to different gate dielectric layers: varying thicknesses (first thickness, second thickness, third thickness), different formation methods (first formation method, second formation method, third formation method), and potentially different materials. These parameter changes enable each transistor type to operate at its optimal voltage range while the systematic approach to parameter differentiation manages the overall device complexity
3Manufacturing precision
If deep trench isolations are used to separate voltage regions, then transistor performance uniformity is improved, but manufacturing complexity increases
Solution Approach 1:
The chip is divided into distinct isolation regions separated by deep trench isolation structures. Each region (first isolation region, second isolation region, third isolation region) is completely isolated from others, ensuring that process variations in one region do not affect transistor performance in other regions. This segmentation maintains performance uniformity within each voltage type while the modular isolation structure manages manufacturing complexity
Solution Approach 2:
Each isolation region is designed with local quality characteristics: first deep trench isolation for high voltage transistors, second deep trench isolation for middle voltage transistors, and third deep trench isolation for low voltage transistors. Each isolation structure is optimized for its specific voltage requirements, ensuring uniform performance within each region while the overall structure remains manageable through systematic local optimization
Data Source
AI summary
A structure with a high voltage transistor, a middle voltage transistor and a low voltage transistor includes a substrate. The substrate includes a high voltage region, a middle voltage region and a low voltage region. A high voltage transistor is disposed within in the high voltage region. The high voltage transistor includes a first gate dielectric layer embedded in the substrate, and a first gate structure disposed on the first gate dielectric layer. A middle voltage transistor is disposed in the middle voltage region. The middle voltage transistor includes a second gate dielectric layer embedded in the substrate. A second gate structure is disposed on the second gate dielectric layer, wherein a thickness of the second gate structure is greater than a thickness of the first gate structure.