Multi-Vt Semiconductor Devices Using Dipole-Modified Gate Dielectrics
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Solution Overview
Problem
The challenge in developing semiconductor devices with multiple threshold voltages (multi-Vt devices) is the lack of sufficient space for additional material layers, which impedes scaling down and affects device performance, particularly channel resistance (Rch).
Innovation Solution
A method for forming semiconductor devices with multiple threshold voltages by using a dipole layer to modify the gate dielectric layer, allowing for fine-tuning of threshold voltages without occupying additional space, involving processes like thermal drive-in to diffuse dipole elements into the gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional material layers are added to provide multiple threshold voltages, then threshold voltage tuning capability is improved, but device volume and complexity increase
Solution Approach 1:
The dipole layer is merged with the gate dielectric layer to form an integrated structure. The dipole elements are incorporated within the gate dielectric layer itself rather than being separate additional layers, thereby providing multiple threshold voltages without increasing overall device volume.
Solution Approach 2:
The dipole layer is nested within the gate dielectric layer. The dipole elements are positioned inside the gate dielectric structure, allowing the threshold voltage tuning function to be embedded within the existing gate structure without requiring additional external space.
2Adaptability or versatility
If additional material layers are added to provide multiple threshold voltages, then threshold voltage tuning capability is improved, but device complexity increases
Solution Approach 1:
The dipole layer is merged with the gate dielectric layer to form an integrated structure. The dipole elements are incorporated within the gate dielectric layer itself rather than being separate additional layers, thereby providing multiple threshold voltages without increasing overall device volume.
Solution Approach 2:
The gate dielectric layer serves multiple functions: it provides electrical insulation between the gate electrode and channel, and simultaneously hosts the dipole elements that enable threshold voltage tuning. This multi-functionality reduces the need for separate dedicated threshold voltage control structures.
3Productivity
If spacing between features is reduced for scaling, then production efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The dipole elements are selectively positioned within the gate dielectric layer at specific locations corresponding to different transistor regions. This local differentiation allows different threshold voltages to be achieved in different areas without requiring additional processing steps or reduced spacing between features.
Solution Approach 2:
The threshold voltage is controlled by changing the concentration and distribution of dipole elements within the gate dielectric layer. By adjusting the dipole element density and positioning, different threshold voltages are achieved through material composition changes rather than structural changes, maintaining spacing and simplifying manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of multi-Vt devices with improved threshold voltage tuning and reduced channel resistance, enhancing device performance without increasing volume requirements.
Implementation Method 1
thermal drive-in to diffuse dipole elements into the gate dielectric layer
Data Source
AI summary
A method includes receiving a structure including a first region and a second region, forming a dielectric layer over the first region and the second region, forming a first patterned layer of a first dipole material on the dielectric layer in the first region, performing a first thermal drive-in operation to drive the first dipole material into the dielectric layer, forming a second patterned layer of a second dipole material on the dielectric layer in the second region, performing a second thermal drive-in operation to drive the second dipole material into the dielectric layer, performing a thermal operation to adjust distribution of the first dipole material or both the first and the second dipole materials in the dielectric layer, and forming a gate electrode layer over the dielectric layer. A portion of the first region overlaps with the second region.