Multi-VT Sensing by Varying Bit Line Voltage
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Solution Overview
Problem
Current NAND flash memory technologies face challenges in efficiently verifying multiple programming states due to increased variability in transistor characteristics over process, voltage, and temperature variations, leading to longer program verify cycles and reduced efficiency.
Innovation Solution
The method involves concurrently verifying two or more memory cell threshold voltage levels by applying different bit line voltages to memory cells connected to a common word line, allowing for simultaneous verification of multiple programming states, thereby reducing the number of program verify cycles required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential verification method is used, then verification accuracy is maintained, but program verify cycle time increases
Solution Approach 1:
The patent divides the memory cells into multiple groups (first group, second group, etc.) and applies different bit line voltages to each group simultaneously. This segmentation allows parallel verification of multiple threshold voltage levels, reducing the sequential verification steps and overall cycle time while maintaining verification accuracy through targeted voltage application to each group.
Solution Approach 2:
The patent dynamically adjusts bit line voltages based on the specific threshold voltage levels being verified. By applying different voltages (first bit line voltage for first threshold voltage, second bit line voltage for second threshold voltage) to different memory cell groups, the system adapts the verification process to handle multiple programming states efficiently, reducing total verification time.
2Productivity
If multiple threshold voltage levels are verified sequentially, then measurement precision is maintained, but productivity decreases
Solution Approach 1:
Memory cells are segmented into distinct groups, each targeted with specific bit line voltages corresponding to their intended threshold voltage levels. This allows simultaneous verification of multiple threshold voltage levels across different groups, increasing throughput while maintaining precision through dedicated voltage application to each group.
Solution Approach 2:
The patent changes the bit line voltage parameter dynamically during verification - applying a first bit line voltage level for verifying first threshold voltage levels, and a second bit line voltage level for verifying second threshold voltage levels. This parameter variation enables parallel verification of multiple states, improving productivity while preserving measurement precision through appropriate voltage selection for each threshold level.
Data Source
AI summary
Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell threshold voltage levels may be concurrently verified by applying a word line voltage to a plurality of memory cells, applying two or more different bit line voltages to the plurality of memory cells, and sensing the plurality of memory cells while the two or more different bit line voltages are applied to the plurality of memory cells. The bit line voltages applied during the program verify operation may allow a first set of the plurality of memory cells to be sensed at a first voltage level while a second set of the plurality of memory cells are sensed at a second voltage level different from the first voltage level.