Multi-Wafer Bonded Chip Formation for Parallel FEOL-BEOL Processing
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges with high throughput and cycle time, leading to increased product development costs and limitations in back-end processes that must avoid impacting front-end structures, necessitating a more efficient method for forming integrated chips.
Innovation Solution
The method involves splitting device processing onto two separate wafers, where one wafer handles front-end processes and the other handles back-end and end-of-line processes, which are then bonded together using a dielectric or metal bonding layer, allowing for independent processing and parallel manufacturing, thereby reducing overall development time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device processing is performed on a single wafer through sequential front-end and back-end processes, then manufacturing complexity is managed, but throughput and cycle time are reduced
Solution Approach 1:
The patent divides the device processing into two separate wafers: Wafer 1 handles front-end processes (FE + Mx metal layers) while Wafer 2 handles back-end and end-of-line processes (Mx+1 through Mx+n metal layers). This segmentation allows parallel processing of both wafers simultaneously, eliminating the sequential bottleneck and significantly improving throughput while reducing overall cycle time.
Solution Approach 2:
The patent transitions from a single-wafer sequential process to a multi-wafer parallel process, adding the dimension of spatial parallelism. By stacking multiple wafers and processing them simultaneously in different process stages, the system achieves higher productivity without increasing the complexity of individual process steps.
2Reliability
If back-end processes are performed on the same wafer as front-end processes, then integration is maintained, but front-end structures are impacted negatively
Solution Approach 1:
By separating front-end and back-end processes onto different wafers, the patent protects front-end structures on Wafer 1 from the harsher back-end processing conditions on Wafer 2. This segmentation allows back-end processes to be performed with greater process flexibility and less constraint, while front-end structure integrity is maintained through physical separation.
3Productivity
If multi-wafer parallel processing is implemented, then throughput and productivity are improved, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent manages manufacturing complexity by segmenting the device into two separate wafers, each handling specific process stages. This segmentation allows each wafer to be processed independently through its designated process flow, reducing the complexity of coordinating all processes on a single wafer while maintaining high throughput through parallel processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces development time and cost by enabling parallel processing of wafers, allowing for higher throughput and yield benefits while minimizing the impact on front-end processes, thus enhancing the manufacturing efficiency and cost-effectiveness.
Implementation Method 1
bonding the first wafer with the second wafer... wherein the layer is to bond the one of the layers of the first and second sets
Implementation Method 2
bonding the first wafer with the second wafer... wherein the layer is to bond the one of the layers of the first and second sets
Data Source
AI summary
An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.