3D Multi-Wafer Integration for Shorter Optical Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing fiber optic devices face challenges in increasing bandwidth density and reducing power consumption and heat generation due to long lead wires used for connecting optical engines and switches, which increase resistance and generate heat.
Innovation Solution
A wafer-level stack structure and process are implemented, where high-performance computing ICs, electronic ICs, and photonic ICs are vertically aligned and bonded to form optical engines, minimizing wire connection lengths and eliminating the need for molding materials, thereby reducing power consumption and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If long lead wires are used to connect optical engines and switches, then ease of assembly is improved, but power consumption increases and heat generation worsens
Solution Approach 1:
The patent transitions from planar (2D) substrate mounting to three-dimensional (3D) stacked wafer integration. Multiple wafers containing optical engines and switches are vertically stacked and bonded together, changing the spatial arrangement from horizontal to vertical. This dimensional change dramatically shortens the connection paths between components, reducing wire lengths from millimeters to micrometers, thereby minimizing resistance and power consumption while maintaining assembly feasibility through automated wafer bonding processes
2Ease of operation
If long lead wires are used to connect optical engines and switches, then ease of assembly is improved, but heat generation increases
Solution Approach 1:
By stacking wafers vertically in the third dimension, the patent creates compact three-dimensional integration. The vertical stacking reduces the physical distance between optical engines and switches from long lead wire connections to direct or minimal interconnects within the stacked structure. This dramatically reduces resistive heating while the compact 3D arrangement improves heat dissipation efficiency through reduced thermal path lengths and increased surface area for heat sinking
3Productivity
If geometry size is decreased to increase functional density, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the integrated circuit system into separate functional wafers (optical engine wafers, switch wafers, etc.) that are fabricated independently using standard semiconductor manufacturing processes. Each wafer can be processed, tested, and prepared separately before final stacking. This segmentation allows parallel fabrication of multiple wafers, maintaining high productivity while managing complexity through modular design and independent processing of each wafer layer
Solution Approach 2:
The patent resolves processing complexity by moving from planar integration to three-dimensional stacking. Multiple wafers with reduced geometry sizes are fabricated using established scaling processes, then vertically stacked and bonded. This approach maintains the benefits of small geometry sizes for high functional density while managing complexity through standardized wafer fabrication processes followed by automated bonding and alignment, rather than attempting complex planar integration of all components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases bandwidth density, reduces power consumption, and lowers heat generation by minimizing wire lengths and simplifying the manufacturing process, while maintaining efficient optical signal transmission and heat dissipation.
Implementation Method 1
bonding the first wafer to the second wafer to form a first stacked wafer
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.