Multi-Wafer Vertical Integration for Low-Power Photonic Interconnects
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Solution Overview
Problem
Existing optic device structures face challenges with increased power consumption and heat generation due to long lead wires connecting optical engines and switches, which are separately mounted on substrates, hindering bandwidth density and miniaturization efforts.
Innovation Solution
A wafer-level stack structure is implemented where multiple substrates are bonded and vertically aligned to form optical engines, eliminating the need for separate cutting and bonding of electronic and photonic dies, reducing wire connections and integrating high-performance computing ICs to control optical engines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If optical engines and switches are separately mounted on substrates and connected by long lead wires, then device assembly is simplified, but power consumption increases and heat generation increases
Solution Approach 1:
The patent merges the optical engine and switch into a single integrated photonic circuit chip, eliminating the need for separate mounting and long lead wire connections. This integration directly reduces power consumption and heat generation while maintaining manufacturing feasibility through advanced photonic fabrication processes
2Ease of manufacture
If optical engines and switches are separately mounted on substrates and connected by long lead wires, then device assembly is simplified, but heat generation increases
Solution Approach 1:
The patent merges the optical engine and switch into a single integrated photonic circuit chip, eliminating the need for separate mounting and long lead wire connections. This integration directly reduces power consumption and heat generation while maintaining manufacturing feasibility through advanced photonic fabrication processes
3Quantity of substance
If miniaturization continues to meet bandwidth density demand, then bandwidth density increases, but power consumption and heat generation continue to pose challenges
Solution Approach 1:
The patent merges the optical engine and switch into a single integrated photonic circuit chip, eliminating the need for separate mounting and long lead wire connections. This integration directly reduces power consumption and heat generation while maintaining manufacturing feasibility through advanced photonic fabrication processes
Solution Approach 2:
The patent transitions from planar two-dimensional integration to three-dimensional vertical stacking of photonic and electronic components. This dimensional change enables higher bandwidth density while minimizing interconnect lengths and associated power consumption through vertical integration architecture
4Quantity of substance
If miniaturization continues to meet bandwidth density demand, then bandwidth density increases, but heat generation continues to pose challenges
Solution Approach 1:
The patent merges the optical engine and switch into a single integrated photonic circuit chip, eliminating the need for separate mounting and long lead wire connections. This integration directly reduces power consumption and heat generation while maintaining manufacturing feasibility through advanced photonic fabrication processes
Solution Approach 2:
The patent transitions from planar two-dimensional integration to three-dimensional vertical stacking of photonic and electronic components. This dimensional change enables higher bandwidth density while minimizing interconnect lengths and associated power consumption through vertical integration architecture
5Use of energy by moving object
If wafer-level stack structure is implemented with multiple substrates bonded and vertically aligned, then wire lengths are minimized and power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary alignment and bonding of multiple wafers at the wafer level before dicing into individual devices. This preliminary action enables precise vertical alignment and minimal wire lengths while simplifying subsequent manufacturing steps through standardized wafer-level processing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes power consumption and heat generation while enhancing bandwidth density by minimizing wire lengths and simplifying the fabrication process.
Implementation Method 1
bonding the first wafer to the second wafer to form a first stacked wafer
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.