Multi-Wafer Stack Structure Eliminating Wire Bonding
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Solution Overview
Problem
Traditional multi-wafer stacking methods face limitations in achieving high-density thickness due to the need for wire pressure welding space and the use of costly gold wires, which result in reduced signal transmission speed and increased power loss.
Innovation Solution
A multi-wafer stack structure is developed, eliminating the need for wire bonding by using interconnected metal layers and dielectric layers to form direct electrical connections between wafers, reducing overall thickness and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for interconnection between multiple wafers, then electrical connection is achieved, but the overall thickness increases due to wire pressure welding space requirements
Solution Approach 1:
The patent merges the interconnection function into the substrate structure itself by forming conductive vias and metal layers directly within the stacked wafer configuration. This integration eliminates the need for separate wire bonding operations and reduces the overall thickness by removing the wire pressure welding space requirement.
Solution Approach 2:
The patent transitions from three-dimensional wire bonding (requiring vertical space for wire loops and pressure welding) to a planar integrated circuit board-style interconnection approach where conductive paths are formed within the substrate planes and through-thickness vias, significantly reducing the vertical dimension occupied by interconnection structures.
2Reliability
If gold wires are used for interconnection, then electrical connection is achieved, but cost increases and signal transmission speed decreases due to long interconnection lines
Solution Approach 1:
The patent extracts the gold wire interconnection element from the system and replaces it with conductive traces formed directly in the substrate. This removal of the wire intermediary eliminates the associated costs, reduces parasitic inductance and resistance, and shortens the signal path length, thereby reducing power loss and improving signal transmission speed.
Solution Approach 2:
The patent introduces a new intermediary structure - the integrated conductive via and trace system within the substrate - that provides a more efficient electrical connection path compared to external wire bonding. This intermediary structure reduces the interconnection length and improves signal integrity while lowering power loss.
3Reliability
If traditional wire bonding is used, then interconnection is achieved, but device complexity increases due to additional substrate processing requirements
Solution Approach 1:
The patent combines the interconnection structure formation with the substrate manufacturing process itself. Conductive vias and metal traces are formed as integral parts of the substrate fabrication sequence, eliminating the need for separate wire bonding operations and associated complex processing steps such as wire alignment, bonding, and trimming.
Data Source
AI summary
A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.