Multi-Wafer Stacking Structure Without Leads
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Solution Overview
Problem
Traditional multi-wafer lead interconnection methods face limitations in thickness due to the need for lead bonding, resulting in increased overall thickness, high costs, reduced signal transmission speed, and increased power loss, as well as an inability to accommodate the growing demand for high-density bonding pads.
Innovation Solution
A multi-wafer stacking structure that eliminates the need for leads by using a first and second wafer with dielectric and metal layers bonded together, along with isolated and interconnection layers, to achieve direct electrical connections between wafers without a silicon substrate, reducing thickness and enhancing signal transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lead bonding is used for multi-wafer interconnection, then interconnection among multiple wafers is achieved, but the overall thickness increases and signal transmission speed decreases
Solution Approach 1:
The patent removes the silicon substrate and lead wires from the traditional multi-wafer stacking structure. By extracting these unnecessary components, the overall thickness is significantly reduced while maintaining interconnection functionality through direct wafer-to-wafer bonding with metal layers serving as interconnection elements.
Solution Approach 2:
The patent merges the functions of the silicon substrate, lead wires, and bonding pads into a single integrated structure where metal layers on the wafer surfaces directly provide both structural support and electrical interconnection. This consolidation eliminates intermediate components and reduces overall device thickness.
2Reliability
If lead bonding is used for multi-wafer interconnection, then interconnection is achieved, but power loss increases and signal transmission speed decreases
Solution Approach 1:
The patent replaces the mechanical lead wire bonding system with a direct metal-layer-to-metal-layer contact system. This substitution eliminates the long interconnection paths and contact resistance associated with lead wires, thereby reducing power loss and improving signal transmission speed through direct electrical contact between adjacent wafer metal layers.
3Reliability
If silicon substrate with sharing bonding pads is used, then multi-wafer stacking is supported, but the structure cannot adapt to high-density bonding pad requirements
Solution Approach 1:
The patent transitions from a planar bonding pad arrangement on a silicon substrate to a three-dimensional metal layer structure where multiple metal layers provide multiple interconnection paths. This dimensional change allows for higher bonding pad density by utilizing vertical stacking of metal layers in addition to horizontal arrangement, enabling high-density multi-wafer stacking.
4Reliability
If gold wires are used as leads, then interconnection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive gold wire leads with copper or aluminum metal layers that are deposited directly on the wafer surfaces using standard semiconductor fabrication processes. These metal layers serve as both structural and electrical interconnection elements, eliminating the need for costly gold wires while maintaining interconnection reliability through direct metal-to-metal contact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall device thickness, increases package density, eliminates the need for costly lead materials, and simplifies the manufacturing process while improving signal transmission speed by shortening interconnection distances and reducing parasitic capacitance.
Implementation Method 1
a second wafer, the second wafer including a second substrate, a second dielectric layer and a second metal layer, the first dielectric layer being bonded to the second dielectric layer
Data Source
AI summary
A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.