Multi-Wafer TSV Structure That Avoids Open Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The size reduction of through-substrate vias during dry etching due to hard mask phenomena leads to open circuit issues between wafers, causing semiconductor structure failures.

Innovation Solution

A semiconductor structure design where the through-substrate via passes through and embeds end portions of conductive connection lines, with pin and annular portions arranged to prevent contact and overlap, ensuring electrical connectivity between wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the through-substrate via size is increased to ensure contact with the metal ring, then the reliability of wafer connection is improved, but the manufacturing precision deteriorates due to hard mask phenomenon causing bottom size reduction

Engineering Contradiction:
Improvewafer connection reliabilityVSAvoidvia bottom size control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent removes the metal ring component from the structure, extracting the source of the hard mask problem. By eliminating the metal ring that causes bottom size reduction during etching, the via can maintain its intended dimensions while still achieving reliable electrical connection between wafers through the conductive connection lines embedded in the via

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces conductive connection lines as an intermediary element between the via and the wafers. These conductive lines are embedded in the via body, serving as a mediator that ensures electrical connectivity without requiring the via bottom to contact a metal ring, thus avoiding the hard mask effect while maintaining connection reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260018493A1Semiconductor structure
Publication Date: 2026.01.15 POWERCHIP SEMICON MFG CORP
  • US20260018493A1 patent drawing
  • US20260018493A1 patent drawing
  • US20260018493A1 patent drawing

AI summary

A semiconductor structure includes a plurality of first wafers and a through-substrate via (TSV). The plurality of first wafers include a plurality of conductive connection lines. Each of the conductive connection lines is located in the corresponding first wafer. The through-substrate via passes through the plurality of first wafers and a plurality of end portions of the plurality of conductive connection lines. The plurality of end portions are embedded in the through-substrate via.