Integrated Multi-Width Fin Structures on Single Substrate for Device Density

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Solution Overview

Problem

As semiconductor devices continue to be scaled down, improving device performance without negatively affecting device density is challenging, limiting advancements in integrated circuit manufacturing.

Innovation Solution

Integrating finFET devices with different widths and nanosheet FET devices on a single substrate, where finFETs are optimized for one application and NSFETs for another, allowing concurrent formation using different masking layers to enhance performance and density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor device sizes are scaled down to increase device density, then device density is improved, but device performance deteriorates

Engineering Contradiction:

Improvedevice densityVSAvoiddevice performance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The substrate is segmented into multiple device regions, each containing fin structures with different widths. This allows different device types (e.g., high-performance devices with wider fins and low-power devices with narrower fins) to coexist on the same substrate, resolving the contradiction by enabling performance optimization for specific devices while maintaining high overall density through the scaled-down substrate layout.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different fin width characteristics are assigned to different spatial locations on the substrate. By locally varying the fin width in different device regions, the invention enables each region to have optimized performance characteristics appropriate for its specific function, thereby improving device performance without sacrificing overall device density.

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If multiple fin structures with different widths are integrated on a single substrate, then design flexibility and device performance are improved, but manufacturing complexity increases

Engineering Contradiction:

Improvedesign flexibilityVSAvoidmanufacturing complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Masking structures with different patterns are formed in advance before the fin structures are created. These pre-formed masking structures define the different fin width regions, allowing the subsequent fin formation process to simultaneously create multiple fin width types in a single step, thereby reducing manufacturing complexity despite the increased design flexibility.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Masking structures serve as intermediary elements that enable the formation of fin structures with different widths. By using these masking intermediaries, the invention can translate complex design requirements for multiple fin widths into a manufacturable process, bridging the gap between design flexibility and manufacturing feasibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250301777A1Integration of multiple fin stuctures on a single substrate

Publication Date: 2025.09.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first semiconductor fin structure and a second semiconductor fin structure laterally adjacent to the first semiconductor fin structure. An isolation structure is around the first and second semiconductor fin structures. A first height of the isolation structure along a sidewall of the first semiconductor fin structure is less than a second height of the isolation structure along a sidewall of the second semiconductor fin structure.