Multi-Width FinFET Structure for SRAM Noise Margin and Speed
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Solution Overview
Problem
Existing FinFET SRAM devices face challenges related to cell write margins and chip speeds, particularly due to reduced static noise margin (SNM) caused by intrinsic threshold voltage (Vt) variations and scaling issues in deep sub-micron integrated circuit technology.
Innovation Solution
The implementation of a FinFET device configuration with specific fin widths, spacings, and gate dielectric thicknesses, allowing for improved gate length scaling and reduced intrinsic Vt fluctuations, thereby enhancing the stability and performance of SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET devices are used to improve gate length scaling and reduce intrinsic Vt fluctuations, then device stability and short channel control are improved, but cell write margins and chip speeds are degraded
Solution Approach 1:
The patent applies different fin widths to different circuits within the same integrated circuit. Specifically, first circuits (such as SRAM cells requiring high speed) use fins with a first width, while second circuits (such as logic circuits requiring stability) use fins with a second width. This local differentiation allows each circuit to be optimized for its specific function, resolving the contradiction between device stability and chip speed by enabling high-speed circuits to use wider fins for better performance while stability-critical circuits use narrower fins for improved short-channel control.
2Quantity of substance
If transistor geometries are scaled down to meet performance requirements, then device density is improved, but static noise margin is reduced due to intrinsic threshold voltage variations
Solution Approach 1:
The patent changes the fin width parameter to compensate for threshold voltage variations caused by scaling. By adjusting the fin width (a geometric parameter), the patent optimizes the balance between device density and static noise margin. Wider fins provide better control over threshold voltage and improve SNM, while still maintaining high device density through optimized spacing and layout arrangements.
3Use of energy by moving object
If Vcc is scaled to lower voltage to improve power efficiency, then power consumption is reduced, but static noise margin is further reduced
Solution Approach 1:
The patent uses different fin widths in different circuits to compensate for the reduced static noise margin caused by lower Vcc scaling. Circuits that are more sensitive to noise (such as SRAM cells) can use wider fins to maintain adequate noise margins even at lower supply voltages, while other circuits can use narrower fins to maintain power efficiency. This allows the system to operate at lower voltages overall while maintaining reliability in critical circuits.
Data Source
AI summary
An IC structure includes first, second, and third circuits. The first circuit includes a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit includes a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit includes a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin.