Multi-Width Instruction Issue in Parallel Slice Processor

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Solution Overview

Problem

Existing processor designs face limitations in throughput due to resource bottlenecks when pipelines are busy, and they often support only a single instruction width, restricting the types of instructions that can be executed, which hampers performance in handling diverse workloads.

Innovation Solution

A circuit arrangement with multiple parallel execution slices that can execute multi-width instructions by using early issue notification signals to prepare slave slices for issuance, allowing concurrent execution across multiple slices, thereby supporting arbitrary instruction assignment and enhancing flexibility in handling various workloads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple pipelines are allocated for execution of different instruction streams, then program execution can continue during conditions when a pipeline is busy, but resources may still be tied up for pipelines that are busy, and when all the pipeline(s) assigned to an instruction stream are busy, the instruction stream may become stalled, reducing the potential throughput of the processor core

Engineering Contradiction:

Improveprocessor throughputVSAvoidresource tie-up time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The processor core is divided into multiple independent execution slices (first execution slice, second execution slice, etc.), each capable of executing instructions from different instruction streams simultaneously. This segmentation allows parallel execution of multiple instruction streams without blocking, as each slice can independently fetch and execute instructions without resource conflicts, thereby eliminating the stall condition described in the contradiction.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The issue logic in each execution slice is configured to queue instructions in advance before they are needed for execution. By pre-queuing instructions and preparing the execution slices ahead of time, the system ensures that when a slice becomes available, instructions are already ready for immediate execution, preventing resource tie-up and maintaining continuous processing flow.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If specific resources and pipelines are allocated for execution of different instruction streams, then multiple pipelines allow program execution to continue during conditions when a pipeline is busy, but resources may still be tied up for pipelines that are busy, reducing the potential throughput of the processor core

Engineering Contradiction:

Improveinstruction stream handling capabilityVSAvoidprocessor throughput

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

Each execution slice is designed as a universal unit that can execute various types of instructions from different instruction streams. The execution slices are not dedicated to specific instruction types but can dynamically handle different instruction streams based on availability and requirements, providing both adaptability and high throughput by efficiently utilizing all slices for productive work.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically assigns instruction streams to execution slices based on real-time availability and workload requirements. The issue logic in each slice independently manages its instruction queue and execution timing, allowing flexible and adaptive resource allocation that maximizes throughput while maintaining the ability to handle diverse instruction streams.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If instructions are limited to supporting a single instruction width such as 32-bits, 64-bits, 128-bits, etc., then the processor design is simplified, but the processor is limited in terms of the different types of instructions that may be supported

Engineering Contradiction:

Improveinstruction width supportVSAvoidprocessor design complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multi-width instructions are segmented into smaller portions that can be handled by individual execution slices. For example, a 128-bit instruction is divided into multiple 64-bit or 32-bit segments that can be processed by different slices in parallel. This segmentation allows the processor to support various instruction widths without requiring each slice to handle the full width, thereby increasing versatility while keeping individual slice designs relatively simple.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple execution slices are merged to collectively handle multi-width instructions. By combining the capabilities of multiple slices, the processor achieves support for various instruction widths (32-bit, 64-bit, 128-bit, etc.) through coordinated operation of the slices, each contributing its portion of the instruction processing capability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9996359B2Fast multi-width instruction issue in parallel slice processor

Publication Date: 2018.06.12 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.