Multi-Window Memory Device Addressing 2TB Capacity Limit
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Solution Overview
Problem
Current memory devices, such as SD cards and eMMC devices, are limited to a maximum storage capacity of 2 terabytes due to the 32-bit address argument, which restricts the number of unique memory addresses, making it difficult to store increasing amounts of high-capacity data like 4K videos and health data over extended periods.
Innovation Solution
The implementation of a multi-window memory device with a continuous memory address space that exceeds the traditional 2 TB limit by using data storage windows, allowing for a 64-bit addressable space through a 32-bit memory device, enabling higher storage capacities by dynamically shifting the data storage window and using window index values to manage multiple memory locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the 32-bit address argument is used in command frames, then compatibility with legacy systems is maintained, but storage capacity is limited to 2 terabytes
Solution Approach 1:
The patent divides the address space into multiple 2TB windows, each accessible through a 32-bit address. By segmenting the total address space into contiguous windows, the system maintains 32-bit addressing for each window while achieving 64-bit equivalent capacity. The memory device controller manages window selection based on the highest non-zero bit of the address, allowing seamless access across window boundaries without requiring 64-bit addresses for each individual window.
Solution Approach 2:
The patent introduces a new dimension to address space by adding a window index component. Instead of using a single 32-bit address, the system combines a 32-bit address with a window index (stored in additional bits) to achieve 64-bit addressing capability. This dimensional extension allows the system to access beyond the 2TB limit while maintaining backward compatibility with 32-bit addressing mechanisms for each individual window.
2Quantity of substance
If sector size is increased from 512 bytes to 4096 bytes, then storage capacity increases, but compatibility with existing systems deteriorates
Solution Approach 1:
The patent maintains 512-byte sector sizes within each window to ensure compatibility with existing systems and command frame formats. By keeping the fundamental sector size unchanged and only extending the address space through windowing, the system achieves higher capacity without compromising compatibility with legacy devices and protocols that expect 512-byte sectors.
3Quantity of substance
If multiple data storage windows are implemented, then addressable storage capacity exceeds 2 TB limit, but device complexity increases
Solution Approach 1:
The memory device controller automatically manages window selection based on the address bits of incoming commands. The controller determines which window to access by examining the highest non-zero bit of the address, eliminating the need for explicit window selection commands from the host. This self-service approach simplifies the interaction interface while maintaining sophisticated window management internally.
Solution Approach 2:
The patent merges multiple 2TB address spaces into a single continuous 64-bit address space through windowing. By combining the window index with the 32-bit address, the system presents a unified address space to the host device, simplifying the interface while enabling access to capacity beyond the individual window limit. The host sees a continuous address space rather than discrete windows, reducing operational complexity.
Data Source
AI summary
A memory device comprises a first plurality of addressable memory locations associated with a first data storage window and a second plurality of addressable memory locations associated with a second data storage window. The memory device includes a controller that receives requests from a host device to identify the first data storage window and the second data storage window. The controller receives requests to assign a first window index value to the first data storage window and to assign a second window index value to the second data storage window. The controller receives memory commands from the host device that indicate the first window index value and at least one address. The controller accesses, based at least on the first window index value, a location associated with the at least one address within the first plurality of addressable memory locations.