Multi-Wire Clock Recovery Circuit for Jitter-Tolerant Data Sampling
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Solution Overview
Problem
Existing clock and data recovery circuits in multi-wire communication systems face challenges with jitter tolerance and scalability, particularly in minimizing analog delays and handling inter-lane skew and data transition glitches, which affect transmission speed and accuracy.
Innovation Solution
A receiver circuit comprising line interfaces, clock extraction circuits, and negative hold time logic circuits that compare and delay signals to generate a clock signal, using comparators, set-reset latches, and analog delay devices to filter out jitter and ensure symbol transitions are used to recover clock and data signals across multiple wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock information is embedded by causing symbol transitions at every symbol cycle, then skew between clock and data signals is minimized and PLL is eliminated, but unintended spike pulses appear on recovered clock signal due to inter-lane skew and data transition glitches
Solution Approach 1:
The patent converts harmful spike pulses generated by data transitions into useful clock signal edges. By detecting transitions on multiple data lanes and using them to trigger clock generation, the circuit transforms what would be noise into the desired clock signal, while filtering mechanisms eliminate remaining harmful artifacts
Solution Approach 2:
The patent introduces intermediary elements including a transition detection circuit that mediates between raw data transitions and clock generation, and a filtering mechanism that acts as an intermediary to remove spike pulses while preserving valid clock edges. These intermediaries isolate the harmful effects from the final clock output
2Productivity
If multiple data signals are used for high-speed transmission, then transmission speed increases, but inter-lane skew and data transition glitches affect clock recovery stability
Solution Approach 1:
The patent segments the clock recovery function into separate processing paths for each data lane, with individual transition detection circuits for each lane. This segmentation allows independent handling of skew in each lane while maintaining overall system performance through coordinated processing of all lanes
Solution Approach 2:
The patent merges transition detection results from multiple data lanes into a unified clock signal. By combining information from all lanes and using majority voting or logical OR operations, the circuit achieves robust clock recovery that tolerates individual lane variations and skew
3Reliability
If conventional clock recovery circuits are used, then clock signal can be recovered, but the circuits are not tolerant to jitter and are sensitive to intermediate or undeterminable data signal states
Solution Approach 1:
The patent implements self-service mechanisms where the clock recovery circuit uses its own output clock signal to control the sampling and detection process. The recovered clock automatically regulates the timing of transition detection, creating a self-synchronizing system that is inherently tolerant to jitter without requiring external phase-locked loops
Solution Approach 2:
The patent changes the operating parameters of the recovery circuit by using data transition edges themselves as clock triggers rather than relying on separate clock signals. This parameter change allows the circuit to adapt dynamically to varying data rates and timing conditions while maintaining jitter tolerance through the inherent stability of the transition-based triggering mechanism
Data Source
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AI summary
A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.