Pulse-Based Multi-Wire Clock Recovery With Reduced Skew
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current communication systems face challenges in reliably recovering clock and data signals from multi-wire interfaces that employ pulse-based signaling, particularly in complex and dynamic signaling environments, where existing methods struggle to efficiently decode information and maintain synchronization.
Innovation Solution
A clock recovery circuit is introduced, comprising input latches, combinational logic, a delay circuit, and output flip-flops, which processes pulses from a multi-wire interface to generate a receive clock signal. This circuit includes a one-shot circuit to fix pulse duration and a counter to count transitions, enabling the recovery of clock and data signals by transcoding multi-digit numbers expressed in various bases, such as ternary or septenary, from pulse-encoded signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate clock channels and phase-locked loops are used for clock and data recovery, then clock and data signals can be recovered, but the system complexity increases and skew between clock and data signals occurs
Solution Approach 1:
The patent combines the clock recovery and data recovery functions into a single integrated circuit block. The clock recovery unit and data recovery unit share common components including the delay-locked loop, voltage-controlled delay line, and sampling mechanism. This merging eliminates the need for separate clock channels and independent phase-locked loops, reducing system complexity while maintaining reliable clock and data signal recovery through unified control and synchronization
2Reliability
If traditional separate clock channels and phase-locked loops are used, then clock and data signals can be recovered, but skew between clock and data signals increases
Solution Approach 1:
By merging clock and data recovery into a single integrated unit with shared delay-locked loop and sampling circuitry, the patent ensures that clock and data paths experience identical timing variations and delays. This unified architecture eliminates differential skew that occurs in separate channels, as both clock and data signals pass through the same physical path and processing stages, achieving precise synchronization without time loss
Solution Approach 2:
The patent employs feedback mechanisms where the recovered clock signal is fed back to control the voltage-controlled delay line and sampling timing. The delay-locked loop continuously adjusts the sampling phase based on feedback from the data signal transitions, ensuring that the sampling clock remains precisely synchronized with the incoming data, thereby minimizing skew through active correction
3Reliability
If more interconnects and device pins are used for separate clock and data channels, then signal transmission is achieved, but the number of interconnects and pin count increases
Solution Approach 1:
The patent merges clock and data transmission into a single integrated channel where the same physical interconnect carries both clock and data signals. The integrated recovery circuit processes both signals simultaneously using shared components, eliminating the need for separate dedicated clock lines and data lines. This approach maintains reliable signal transmission through proper timing control while significantly reducing the quantity of interconnects and device pins required
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.