Multi-Wire Clock Recovery Circuit for Skew and Glitch Filtering
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Solution Overview
Problem
Clock recovery from multiple data signals is hindered by inter-lane skew and data state transition glitches, leading to unintended spike pulses in the recovered clock signal, which existing technologies struggle to effectively mitigate without increasing analog delays or requiring complex de-skewing circuitry.
Innovation Solution
A clock recovery circuit comprising a receiver circuit and a clock extraction circuit that decodes differentially encoded signals, using feedback delayed state transition signals to obtain the clock signal while compensating for skew and masking glitches, employing components like comparators, set-reset latches, analog delay devices, and one-shot logic to filter and delay signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock recovery is performed from multiple data signals using conventional methods, then clock signal can be extracted, but unintended spike pulses appear due to inter-lane skew and data state transition glitches
Solution Approach 1:
The patent introduces an intermediary filtering mechanism between the multiple data signals and the clock recovery process. The filtering logic acts as a mediator that selectively passes valid clock transitions while blocking spike pulses caused by inter-lane skew and glitches, thereby improving clock signal quality without requiring complex de-skewing circuitry
Solution Approach 2:
The patent extracts only the essential clock information from the data signals by identifying specific transition patterns that represent valid clock events. By taking out and isolating these valid transitions while leaving out the harmful spike pulses, the circuit recovers a clean clock signal without needing to process all signal variations
2Measurement precision
If de-skewing circuitry is added to compensate for inter-lane skew, then clock recovery accuracy improves, but device complexity increases
Solution Approach 1:
The patent employs a self-service approach where the clock recovery circuit automatically compensates for inter-lane skew through its inherent filtering logic and feedback mechanisms. The circuit serves itself by detecting and correcting timing variations without requiring external de-skewing circuitry, thereby maintaining high accuracy while minimizing complexity
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor the recovered clock signal and adjust the filtering logic accordingly. This feedback loop enables the circuit to adapt to varying skew conditions dynamically, maintaining accurate clock recovery without adding complex fixed de-skewing circuitry for all possible scenarios
3Stability of the object's composition
If analog delay devices are used to compensate for skew, then timing alignment improves, but signal delay increases
Solution Approach 1:
The patent applies preliminary filtering and validation actions to identify valid clock transitions before they are delayed by analog delay devices. By pre-processing the signals to mark valid transitions, the circuit can apply minimal necessary delay only to those specific signals, achieving timing alignment while minimizing overall signal delay
Data Source
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AI summary
A method for performing multi-wire signaling decoding is provided. A raw symbol spread over a plurality of n wires is received via a plurality of differential receivers. The raw symbol is converted into a sequential number from a set of sequential numbers. Each sequential number is converted to a transition number. A plurality of transition numbers is converted into a sequence of data bits. A clock signal is then extracted from the reception of raw symbols.