Multi-Wire FEC Permutation for Low-Latency Burst Error Robustness
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, conventional methods of serialization and deserialization introduce latency, and existing Forward Error Correction (FEC) methods struggle to effectively manage error correction across multiple parallel channels, leading to increased communication latency and vulnerability to burst errors.
Innovation Solution
The proposed solution involves permuting the transmission order of FEC-encoded packets across multiple sub-channels in a multi-wire bus, using a permuter function to distribute FEC-encoded bits in a cyclically varying order, ensuring that sequential streams from each FEC encoder are transmitted to different sub-channel encoders, thereby reducing latency and enhancing error correction robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional serialization and deserialization methods are used in high-speed chip-to-chip communication systems, then the system structure is simple, but communication latency increases
Solution Approach 1:
The patent divides the communication system into multiple parallel sub-channels, each handling a portion of the data stream. By segmenting the data flow across multiple channels and processing them simultaneously, the system reduces overall latency without requiring a complete redesign of the serialization/deserialization architecture.
Solution Approach 2:
The patent transitions from single-channel sequential processing to multi-channel parallel processing, adding a spatial dimension to data transmission. This dimensional change allows multiple data streams to be transmitted simultaneously, reducing latency while maintaining manageable system complexity through structured channel management.
2Reliability
If existing FEC methods are applied to multiple parallel channels, then error correction coverage is provided, but communication latency increases and vulnerability to burst errors remains
Solution Approach 1:
The patent applies FEC encoding to each sub-channel independently before transmission, performing error correction preparation in advance. This preliminary action allows the system to handle errors efficiently during transmission without requiring additional latency for error correction processing after data arrival.
Solution Approach 2:
The patent segments the overall error correction task into independent FEC operations on each sub-channel. This segmentation allows parallel error correction processing, reducing the total time required compared to sequential error correction on a single aggregated channel.
3Reliability
If sequential streams from each FEC encoder are transmitted on the same sub-channel, then transmission is simple, but the system becomes vulnerable to burst errors
Solution Approach 1:
The patent distributes sequential streams from different FEC encoders across multiple sub-channels rather than concentrating them on a single channel. This segmentation ensures that burst errors affecting one sub-channel do not corrupt multiple data streams simultaneously, improving robustness while maintaining structured transmission management.
Solution Approach 2:
The patent applies different transmission patterns to different sub-channels, with each sub-channel carrying streams from specific FEC encoders. This local differentiation optimizes error distribution across the system, making the overall transmission more resilient to localized burst errors without requiring complex global reconfiguration.
Data Source
AI summary
Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.