Multi-wire Signaling with Matched Propagation Delay

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Solution Overview

Problem

Multi-wire signaling schemes, such as C-PHY, face issues with jitter due to timing skew between symbols received on different wire pairs, leading to suboptimal signaling and increased jitter, which affects data transmission quality.

Innovation Solution

The introduction of delay elements, either passive or active, is used to balance the signal propagation times across different wire pairs in a multi-wire channel by adding delay to specific wires, ensuring that each unique wire pair has approximately equal signal propagation time within a threshold margin, thereby reducing jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-wire signaling is used to increase data transmission capacity, then productivity is improved, but timing skew between wire pairs increases causing jitter

Engineering Contradiction:
Improvedata transmission capacityVSAvoidtiming accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by introducing delay elements specifically to wires with faster propagation speeds. Instead of treating all wires uniformly, the solution selectively modifies individual wires to achieve balanced timing across the multi-wire channel, thereby reducing jitter while maintaining high data transmission capacity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the propagation delay parameter of specific wires by inserting delay elements. This parameter modification equalizes the signal arrival times across different wire pairs, resolving the timing skew issue that arises from using multiple wires for increased data transmission capacity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If delay elements are added to balance propagation times, then timing accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies partial action by introducing delay elements only to the extent necessary to equalize propagation times. Rather than adding complex synchronization circuits to all wires, the solution selectively applies minimal delay to specific wires, achieving timing accuracy with reduced additional complexity

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The delay elements act as intermediary components that mediate the timing differences between wire pairs. These intermediaries absorb the propagation time variations without requiring complex redesign of the entire multi-wire signaling system, thereby improving timing accuracy with manageable complexity increase

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3162012B1Multi-wire signaling with matched propagation delay among wire pairs
Publication Date: 2023.08.09 QUALCOMM INC
  • EP3162012B1 patent drawingFigure 1
  • EP3162012B1 patent drawingFigure 2
  • EP3162012B1 patent drawingFigure 3

AI summary

In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.