Multi-Word Transfer Instruction for Processor Memory Subsystems
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Solution Overview
Problem
Modern processors with a large number of registers face inefficiencies in multi-word data transfer due to limitations in instruction formats, leading to larger program code sizes and lower performance when using sequences of one-word transfer instructions.
Innovation Solution
A multi-word transfer instruction is introduced that specifies a register group, selection mask, and base register for consecutive memory locations, along with additional modes for address updates and modifications, allowing for simultaneous transfer of multiple words between processor registers and memory subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a sequence of one-word transfer instructions is used to transfer multiple words, then the transfer can be performed with simple instruction formats, but the program code size increases and performance decreases
Solution Approach 1:
The patent combines multiple one-word transfer operations into a single multi-word transfer instruction. The instruction format includes fields for specifying a base register, offset, and the number of words to transfer, allowing multiple memory locations to be accessed in one instruction execution cycle, thereby improving transfer efficiency without requiring complex instruction formats.
Solution Approach 2:
The multi-word transfer instruction is designed to handle various transfer scenarios (different numbers of words, different base addresses, different offsets) through a unified instruction format. This universal approach allows the same instruction type to perform multiple transfer operations by varying its parameters, reducing the need for multiple specialized instructions.
2Productivity
If a full register selection mask is used to specify multiple registers in one instruction, then multiple words can be accessed simultaneously, but the instruction format becomes too large for processors with many registers
Solution Approach 1:
The patent segments the register specification into two parts: a base register that defines the starting memory address, and an offset that specifies the relative position. This segmentation avoids the need for a full register selection mask while still enabling access to multiple memory locations. The base register and offset combination can address multiple words without requiring bits for each individual register selection.
Solution Approach 2:
Instead of using a flat register selection mask that requires N bits for N registers, the patent introduces a two-dimensional addressing scheme using base register plus offset. This dimensional change allows the same number of bits to address a larger space of memory locations, effectively enabling multi-word transfer without increasing instruction format size proportionally to the number of registers.
3Ease of manufacture
If multiple consecutive memory locations are accessed using one-word instructions, then the implementation is simple, but the program code size becomes larger
Solution Approach 1:
The patent merges multiple one-word transfer instructions into a single multi-word transfer instruction. By specifying the base register, offset, and word count in one instruction, the patent reduces the number of instruction bytes required in the program, directly decreasing program code size while maintaining implementation simplicity through a standardized instruction format.
Data Source
AI summary
A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.