Multi-Work Function Gate Patterns for CMOS Threshold Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is controlling the thickness of barrier layers in metal gate structures with high-k gate insulating layers, which becomes impractical due to the reduced size of semiconductor devices, hindering the control of work function for ultra-thin gate insulating layers and high operation speed requirements.
Innovation Solution
A semiconductor device with multi-work function gate patterns is developed, featuring different metal materials for gate barrier patterns in various transistor areas, allowing for distinct work functions and threshold voltages, enabling precise control through a method that includes forming interfacial and gate insulating layers, barrier layers, and work function metal patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of barrier layers is controlled to adjust work function, then the work function control is achieved, but the manufacturing process becomes impractical due to reduced device size
Solution Approach 1:
The patent applies local quality by using different metal materials for gate barrier patterns in different transistor areas (first gate barrier pattern with first metal material in first transistor area, second gate barrier pattern with second metal material in second transistor area). This allows each region to have optimized local properties (work function) without requiring precise thickness control across the entire structure, thereby maintaining manufacturing feasibility while achieving work function control.
Solution Approach 2:
The patent changes the material parameter (metal type) instead of controlling the dimensional parameter (barrier layer thickness). By selecting different metal materials with different work functions for different gate barrier patterns, the invention achieves work function control through material selection rather than dimensional control, which is more practical for scaled-down devices.
2Speed
If ultra-thin gate insulating layers are used for high operation speed, then operation speed is improved, but control over work function becomes difficult
Solution Approach 1:
The patent uses local quality by implementing different gate barrier patterns (first gate barrier pattern with first metal material, second gate barrier pattern with second metal material) in different transistor areas. This allows independent optimization of work function for each transistor type (e.g., NMOS and PMOS) without being constrained by the ultra-thin gate insulating layer thickness, enabling both high operation speed and precise work function control.
Solution Approach 2:
The patent employs composite materials by combining different metal materials in the gate barrier patterns. The first gate barrier pattern uses a first metal material and the second gate barrier pattern uses a second metal material, creating a composite structure that provides different work functions tailored to different transistor requirements, thereby maintaining control over work function even with ultra-thin gate insulating layers.
3Adaptability or versatility
If different work functions are required for different transistor areas, then transistor performance is optimized, but the gate structure complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple distinct gate barrier patterns (first gate barrier pattern, second gate barrier pattern) corresponding to different transistor areas. Each segmented region uses a different metal material optimized for its specific transistor type, allowing performance optimization without requiring a completely complex multi-layer structure throughout the entire device.
Solution Approach 2:
The patent implements local quality by assigning different metal materials to different gate barrier patterns based on the specific transistor area requirements. The first gate barrier pattern with first metal material serves the first transistor area, while the second gate barrier pattern with second metal material serves the second transistor area, enabling localized performance optimization with relatively simple overall structure.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.