Multi-Write Endurance Coding for Non-Volatile Memory Wear Reduction
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Solution Overview
Problem
Non-volatile memory devices like NAND flash memory have limited endurance due to write amplification, which reduces their lifetime and requires frequent erase operations, as they do not support page erases, leading to increased wear and tear.
Innovation Solution
The integration of multi-write endurance (MWE) coding with error correction codes (ECC) allows for multiple writes to a page without erasure by encoding data in a way that is consistent with the current electrical charge levels of memory cells, minimizing wear and ensuring data reliability through error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC encoding is used without considering current page state, then error correction capability is provided, but write amplification increases and memory cell wear accelerates
Solution Approach 1:
The patent performs preliminary encoding operations to determine compatible codewords before actual writing occurs. The encoder checks the current page state and pre-selects codewords that are consistent with existing data, avoiding subsequent read-modify-write cycles and reducing write amplification while maintaining error correction capability
Solution Approach 2:
The patent introduces an intermediary encoding layer that sits between traditional ECC encoding and the physical write operation. This intermediary layer selects codewords from a constrained set that are compatible with the current page state, acting as a mediator that satisfies both error correction requirements and wear reduction goals
2Reliability
If page erase operations are performed frequently to enable rewriting, then data reliability is maintained, but write amplification increases and memory lifetime decreases
Solution Approach 1:
The patent segments the codeword space into multiple compatible sets based on the current page state. Instead of treating the page as a monolithic unit requiring full erasure, the encoding process selectively chooses from segmented codeword sets that are compatible with existing data portions, enabling incremental updates without full page erasures
Solution Approach 2:
The patent changes the parameter space of valid codewords based on the current page state. By dynamically adjusting which codewords are considered valid (consistent with current electrical charge levels), the system enables rewriting without erasure, improving write efficiency while maintaining data reliability through constrained coding
3Speed
If codewords are selected without consistency checks, then writing speed is faster, but errors propagate and data reliability decreases
Solution Approach 1:
The patent performs preliminary consistency checks during the encoding phase before the actual write operation. By pre-verifying that selected codewords are consistent with the current page state, the system ensures data reliability without requiring slower post-write verification or read-modify-write cycles
Solution Approach 2:
The patent implements feedback from the current page state to the codeword selection process. The encoder receives feedback about existing data patterns and electrical charge levels, and uses this feedback to select appropriate codewords that maintain consistency, ensuring reliability while maintaining writing speed through efficient feedback-driven selection
Data Source
AI summary
Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page.