Multi-Write Read-Only Memory Array Vertical Capacitor Stacking
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in reducing the area of the gate capacitor, which leads to higher overall resistance and lower capacitance, affecting stability, reliability, power consumption, storage density, and read speed.
Innovation Solution
A multi-write read-only memory array is designed with a configuration that includes multiple common-source lines, word bit lines, and sub-memory arrays, where each memory cell is coupled to two common-source lines and two word bit lines, reducing the capacitor area and overall resistance while increasing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the gate capacitor is increased to improve stability and reliability, then the overall resistance becomes higher and the capacitance becomes lower
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked capacitor structure. The gate capacitor is formed by stacking multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) vertically, utilizing the vertical dimension to increase capacitance without expanding the horizontal area. This dimensional change allows the capacitor to achieve higher capacitance density while maintaining a compact footprint.
Solution Approach 2:
The patent implements a nested structure where conductive layers are stacked within each other to form the gate capacitor. The first conductive layer, second conductive layer, and third conductive layer are nested vertically, with each layer contributing to the overall capacitance. This nested arrangement maximizes the use of vertical space and increases the effective capacitor area without proportionally increasing the device footprint.
2Reliability
If the area of the gate capacitor is increased to improve stability and reliability, then the overall resistance becomes higher
Solution Approach 1:
The patent utilizes vertical stacking of conductive layers to increase capacitance without expanding horizontal dimensions. This dimensional transition reduces the overall resistance by shortening the current path length and decreasing the resistance associated with larger lateral connections, while still achieving the required capacitance through the vertical capacitor structure.
Solution Approach 2:
The patent combines multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) into a single integrated gate capacitor structure. By merging these layers in a vertical stack, the design achieves higher effective capacitance while reducing the overall resistance through parallel conduction paths, thereby improving both reliability and electrical performance.
3Area of moving object
If the area of the gate capacitor is decreased to reduce device size, then the capacitance becomes lower
Solution Approach 1:
The patent solves the capacitance-area tradeoff by transitioning to a vertical stacked capacitor architecture. The gate capacitor utilizes the vertical dimension with multiple stacked conductive layers, enabling high capacitance values to be achieved within a reduced horizontal footprint. This dimensional change decouples the relationship between capacitor area and capacitance, allowing small-area devices to maintain high capacitance.
Solution Approach 2:
The patent employs a nested structure where multiple conductive layers are stacked vertically to form the gate capacitor. This nested arrangement packs multiple capacitor elements into a compact vertical space, achieving high total capacitance within a small device area. The nested configuration allows the capacitor to store more charge without proportionally increasing the device footprint.
Data Source
AI summary
The disclosure describes a multi-write read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell is coupled to the word bit line and the common-source line. The read-only memory includes a field-effect transistor and a capacitor. The source of the field-effect transistor is coupled to the word bit line. The drain of the field-effect transistor is coupled to the common-source line. The capacitor is coupled to the gate of the field-effect transistor and the word bit line.