Multi-Write ROM Array Using Drain-Driven Gate Voltage
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Solution Overview
Problem
Existing read-only memory arrays face challenges in stability, reliability, power consumption, storage density, and read speed due to the large area of gate capacitors, making them less competitive in the market.
Innovation Solution
A multi-write read-only memory array design that reduces the area of capacitors by employing the drain of a field-effect transistor to provide gate voltage, utilizing a semiconductor region with specific conductivity types and heavily-doped areas to form MOSFETs and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the gate capacitor is made larger, then the stability and reliability of the read-only memory are improved, but the cost and area occupation increase
Solution Approach 1:
The patent merges the gate capacitor function with the existing transistor structure by utilizing the transistor's drain region to provide gate voltage. This integration eliminates the need for a separate, large-area gate capacitor while maintaining the stability and reliability requirements through the shared structural components.
Solution Approach 2:
The transistor structure is designed to serve multiple functions: it acts as both the switching element and the voltage source for the gate. The drain region provides gate voltage, making the transistor a multi-functional component that reduces overall area requirements while maintaining memory reliability.
2Area of stationary object
If the area of the gate capacitor is reduced, then the cost and area occupation are reduced, but the stability and reliability may deteriorate
Solution Approach 1:
By combining the gate capacitor functionality into the transistor structure itself, the patent achieves area reduction without compromising reliability. The merged structure ensures that the gate voltage is still reliably provided through the drain region, maintaining memory stability with minimal area occupation.
3Ease of manufacture
If conventional read-only memory structure is used, then manufacturing process is simple, but storage density and read speed are limited
Solution Approach 1:
The patent divides the memory array into multiple sub-memory arrays, each with its own set of memory cells. This segmentation allows for increased storage density by organizing data in smaller, more efficient units while maintaining simple manufacturing processes through standardized cell structures that can be replicated across multiple arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces the area of capacitors, enhancing stability, reliability, and read speed while maintaining competitive market positioning.
Implementation Method 1
The first heavily-doped area and the second heavily-doped area are formed in the semiconductor region, respectively formed on two opposite side of the semiconductor region, which is directly arranged under the first conductive gate, and respectively coupled to the first bit line and the first word common-source line. The first heavily-doped area and the second heavily-doped area have a second conductivity type opposite to the first conductivity type.
Implementation Method 2
The first gate dielectric block, the second gate dielectric block, the third gate dielectric block, and the fourth gate dielectric block are respectively formed on the semiconductor region. The first conductive gate, the second conductive gate, the third conductive gate, and the fourth conductive gate are respectively formed on the first gate dielectric block, the second gate dielectric block, the third gate dielectric block, and the fourth gate dielectric block.
Data Source
AI summary
A multi-write read-only memory array includes word common-source lines, bit lines, and sub-memory arrays. The word common-source lines include a first word common-source line and a second word common-source line. The bit lines include a first bit line and a second bit line. Each sub-memory array includes a first memory cell coupled to the first word common-source line and the first bit line, a second memory cell coupled to the first word common-source line and the second bit line, a third memory cell coupled to the second word common-source line and the second bit line, and a fourth memory cell coupled to the second word common-source line and the first bit line.