Multi-Writing Port Register File Architecture for Pipeline Efficiency
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Solution Overview
Problem
The existing instruction pipeline in processors faces inefficiencies in write-back operations due to conflicts and resource overhead, particularly when execution units have different delays, leading to pipeline blockages and reduced processor performance.
Innovation Solution
The implementation of multiple writing ports, each corresponding to specific execution delays, allows direct access to any register unit, eliminating conflicts and the need for arbitration logic or cache queues, thereby improving write-back efficiency and reducing resource overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single writing port is used in the instruction pipeline, then the device complexity is reduced, but the pipeline efficiency deteriorates due to write conflicts and resource overhead
Solution Approach 1:
The single writing port is segmented into multiple writing ports (first writing port, second writing port, third writing port) that are each coupled to different execution units. This segmentation allows simultaneous write operations from multiple execution units without conflicts, thereby improving pipeline efficiency while maintaining manageable complexity through systematic port allocation.
2Power
If multiple execution units with different execution delays are used, then the processing capability is improved, but the write-back efficiency deteriorates due to timing conflicts
Solution Approach 1:
The writing ports act as intermediaries between execution units and the register file. Each writing port is specifically coupled to execution units with matching execution delays, serving as a mediator that synchronizes data flow timing. This intermediary approach allows multiple execution units with different delays to write back results simultaneously without timing conflicts, maintaining both high processing capability and write-back efficiency.
3Reliability
If arbitration logic and cache queues are added to manage write conflicts, then the reliability of write operations is improved, but the resource overhead increases
Solution Approach 1:
The patent extracts and removes the arbitration logic and cache queues from the system by adopting a multi-writing port architecture. Instead of using complex arbitration mechanisms to manage write conflicts, the system directly provides multiple dedicated writing ports to different execution units, eliminating the need for arbitration logic and cache queues entirely. This extraction maintains write operation reliability through dedicated pathways while significantly reducing resource overhead.
Data Source
Figure 1A~1B
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AI summary
The invention discloses an apparatus and method for writing back an instruction execution result. The apparatus includes: a first writing port (210), coupled between a first execution unit with a first execution delay and a register file, and configured to receive a first execution result from the first execution unit, and to write the first execution result back to a first register unit in the register file based on a first writing address; and a second writing port (212), coupled between a second execution unit with a second execution delay different from the first execution delay and the register file, and configured to receive a second execution result from the second execution unit, and to write the second execution result back to a second register unit in the register file based on a second writing address.