Multi-zone Through Silicon Vias for High-density Microfluidic Chips
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Solution Overview
Problem
The development of massively parallelized microfluidic chips requires Through Silicon Vias (TSVs) with small footprints to enable high-density feature packing, while minimizing debris generation and wafer warping to facilitate bonding with glass substrates.
Innovation Solution
A robust microfabrication strategy involving a stress-relieved SiO2 etch-stop layer and trenches in delivery channels, replacing conventional carrier wafers and allowing for the fabrication of small footprint TSVs with high mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TSVs are made with small footprints to enable high-density feature packing, then device density and throughput are improved, but debris generation and wafer warping increase during manufacturing
Solution Approach 1:
The patent divides the TSV structure into multiple zones with different diameters along the depth axis. The upper zone has a larger diameter that tapers to a smaller lower zone, allowing the via to maintain structural integrity and reduce warping while achieving a small footprint at the surface for high-density packing
Solution Approach 2:
The patent changes the geometric parameters of the TSV by creating a multi-zone structure with varying diameters. This parameter variation allows optimization of both the footprint (for density) and the internal structure (to reduce debris and warping during fabrication)
2Ease of manufacture
If conventional carrier wafers are used during TSV fabrication, then manufacturing process is simplified, but wafer warping and debris generation increase
Solution Approach 1:
The patent removes the conventional carrier wafer from the fabrication process and replaces it with a stress-relieved SiO2 etch-stop layer deposited directly on the silicon substrate. This extraction eliminates the warping and debris issues associated with carrier wafers while maintaining process feasibility
Solution Approach 2:
The patent introduces a stress-relieved SiO2 etch-stop layer as an intermediary between the silicon substrate and the TSV structure. This intermediate layer provides mechanical support during fabrication, prevents warping, and reduces debris generation without requiring a separate carrier wafer
Data Source
AI summary
A method, comprising: etching, in a first surface of a substrate having first and second surfaces spaced from one another along a transverse direction, a plurality of delivery channels such that a delivery channel has a first cross-sectional dimension along a first plane that is perpendicular to the transverse direction; forming an oxide layer on the first surface of the substrate and on inner surfaces of the delivery channels; etching vias in the second surface of the substrate so each via is aligned with a respective one of the delivery channels along the transverse direction; etching droplet generators in the second surface of the substrate such that each droplet generator is in fluid communication with at least one of vias; removing the oxide layer from the first surface of the substrate and the inner surfaces of the delivery channels to place the vias in fluid communication with the delivery channels.