Multi-Antenna Data Converter Clocking for Spectral Alias Management
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Solution Overview
Problem
In multi-antenna communication systems, particularly in 5G cellular networks, the increased number of antenna elements poses challenges in hardware design due to the need for efficient signal processing and filtering, as existing approaches often require equally configured transmit and receive paths for all antenna elements, leading to limitations in managing spectral repetitions and aliases.
Innovation Solution
A communication circuit is designed where each data converter in the system is clocked with a distinct sampling clock frequency, with the clock-signal generation circuit generating sampling clock signals that differ by a non-zero integer multiple of the carrier bandwidth, spreading out spectral repetitions and aliases over a larger frequency range, thereby reducing the need for steep filters and improving signal processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all data converters use the same sampling clock frequency, then the hardware design is simpler and more modular, but spectral repetitions and aliases concentrate at specific frequencies requiring steep filters
Solution Approach 1:
The patent applies local quality by assigning different sampling clock frequencies to different data converters (DACs/ADCs) connected to different antenna elements. Specifically, data converters in different communication units use sampling frequencies that differ by non-zero integer multiples of the carrier bandwidth, causing spectral repetitions and aliases to appear at different frequencies for each converter. This local differentiation spreads harmful spectral components across the frequency spectrum rather than concentrating them, relaxing filter requirements while maintaining modular hardware design.
2Object-affected harmful factors
If different sampling clock frequencies are used for different data converters, then spectral repetitions and aliases are spread out over a larger frequency range, but the clock-signal generation circuit becomes more complex
Solution Approach 1:
The patent implements parameter changes by systematically varying the sampling clock frequency parameter across different data converters. The clock-signal generation circuit generates sampling clock signals with frequencies that differ by non-zero integer multiples of the carrier bandwidth. This structured parameter variation achieves effective spreading of spectral repetitions and aliases while maintaining a manageable clock-generation architecture through regular frequency spacing based on the carrier bandwidth.
3Ease of manufacture
If equally configured transmit and receive paths are used for all antenna elements, then the design is simple and modular, but signal processing efficiency is limited
Solution Approach 1:
The patent applies local quality by configuring data converters in different communication units with different sampling clock frequencies, even though the overall transmit and receive path architecture remains modular and equally configured. This local differentiation in sampling frequencies enables more efficient signal processing by spreading spectral repetitions and aliases, allowing for more effective MIMO and beamforming operations without sacrificing the modular design approach.
Data Source
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AI summary
A communication circuit (20) for communication via multiple antenna elements (10j) of a communication apparatus (2) is disclosed. The communication circuit (20) comprises a plurality of communication units (30j) configured to communicate simultaneously in the same frequency band. Each communication unit (30j) of said plurality of communication units (30j) is arranged to be connected to a separate antenna element (10j) and comprises a data converter (90, 120). The data converters (90, 120) of the plurality of communication units (30j) together form a set of data converters. Furthermore, the communication circuit (20) comprises a clock- signal generation circuit (50) configured to generate a distinct sampling clock signal at a distinct sampling clock frequency (f sj) to each data converter (90, 120) in the set of data converters.