Multi-Band Digital PLL Calibration for Linear Frequency Ramps
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Solution Overview
Problem
Existing Phase-Locked Loops (PLLs), particularly Charge-Pump PLLs, face limitations such as large external analogue filters, noise coupling, limited headroom, and difficulties in testing due to PVT variations, and fail to provide wideband and highly linear frequency ramps, which are essential for frequency modulated continuous wave (FMCW) radar applications.
Innovation Solution
A digital PLL with a multi-band oscillator and memory configured to store control inputs, allowing for calibration mode operations to acquire and store frequency controlled words (FCWs) across bands, providing coarse and fine control inputs to ensure linear frequency ramps, and using a look-up table to adjust control inputs for smooth band transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a Charge-Pump PLL is used to generate frequency ramps, then the PLL can provide frequency synthesis capability, but it requires large external analogue filters and has limited headroom for charge pump and VCO tuning ports
Solution Approach 1:
The patent replaces the traditional charge-pump PLL architecture with a digital PLL that uses a digitally controlled oscillator (DCO) and digital filtering. This substitution eliminates the need for large external analogue filters and charge pump circuits, reducing device complexity while maintaining frequency synthesis capability. The digital filter processes control words to generate DCO tuning values, replacing the analogue filter's frequency selection function.
2Power
If a Charge-Pump PLL is used, then frequency synthesis is achieved, but there is inherent coupling from noisy digital circuits to sensitive analogue nodes such as the VCO tuning voltage
Solution Approach 1:
The patent eliminates the analogue VCO and its sensitive tuning voltage node by using a digitally controlled oscillator. The DCO receives digital control words instead of analogue voltages, completely removing the noise coupling path from digital circuits to analogue nodes. All control signals remain in the digital domain, immune to noise interference.
3Manufacturing precision
If previous digital PLL configurations are used to generate frequency ramps spanning multiple bands, then wide tuning range and fine frequency resolution are achieved, but calibration algorithms are slow and memory consuming
Solution Approach 1:
The patent pre-calculates and stores optimal DCO control words for each frequency band and ramp slope combination in lookup tables during manufacturing. During operation, the system simply retrieves the pre-computed control words based on the desired band and slope, eliminating the need for slow runtime calibration algorithms. This preliminary action transfers the computational burden from runtime to manufacturing time.
Solution Approach 2:
The patent divides the frequency tuning range into multiple bands, each with pre-stored control word tables. The frequency ramp generation is segmented into discrete band transitions, with each band having its own optimized control parameters. This segmentation allows efficient memory organization and fast lookup operations compared to comprehensive calibration algorithms.
4Adaptability or versatility
If frequency ramps span multiple oscillator bands, then wide frequency range is achieved, but discontinuities occur at band transitions reducing linearity
Solution Approach 1:
The patent pre-calculates control word transitions at band boundaries to ensure continuous frequency ramps. The lookup tables store adjusted control words that compensate for oscillator frequency discontinuities at band edges. This preliminary compensation ensures that frequency ramps remain linear and continuous across band transitions without requiring real-time detection or correction.
Data Source
AI summary
A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.