Multibank Coherence Controller for Concurrent Shared Memory Access

The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that automatically monitors and manages cache coherency. The coherency controller includes snoop filter banks, cache tag banks, and memory banks that operate in parallel to detect and resolve coherency issues without software intervention, thereby maintaining reliability while dramatically improving operational efficiency.

The patent introduces a coherency controller as an intermediary component between processing cores and memory devices. This intermediary automatically handles coherency management by intercepting memory requests, checking cache states, and coordinating data access across multiple cores, eliminating the need for inefficient software-based coherency maintenance while preserving data consistency.

The patent implements a feedback mechanism where the coherency controller continuously monitors cache access patterns and memory requests from multiple processing cores. When coherency violations are detected through snoop operations, the controller automatically initiates corrective actions such as cache line invalidation or data synchronization, providing real-time feedback that maintains data coherency while allowing parallel processing to continue.

The patent employs preliminary action by having the coherency controller proactively check cache states and predict potential coherency conflicts before they occur. The snoop filter banks pre-screen memory requests against cached data, and the controller preemptively resolves coherency issues by coordinating data transfers or invalidating stale cache entries before inconsistent data can be accessed, thus maintaining reliability without hindering parallelism.